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參數(shù)資料
| 型號(hào)： | AD73311LARSZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 17/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONT END LP 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 2 |
| 功率（瓦特）： | 50mW |
| 電壓 - 電源，模擬： | 3V |
| 電壓 - 電源，數(shù)字： | 3V |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD73311LARSZ-REEL7DKR |
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AD73311
–24–
REV. B
It is also possible to subsample the DAC—update at a lower rate
than the sampling rate—to reduce the overhead on the DSP.
This, however, results in imaging of the subsampled bandwidth
into the normal bandwidth, which implies that higher perfor-
mance external anti-imaging filtering must be used to eliminate
the images.
The interpolator input also provides a minimum group delay
realization in situations where that is critical. Further reduction
in group delay is possible by accessing the digital sigma-delta
input at the expense of lower attenuation of images due to any
repetition of input samples. Figure 21 shows the spectral
response of the decoder being sampled at 64 kHz with its inter-
polator bypassed.
FREQUENCY – kHz
0
–140
032
510
15
20
25
30
–20
–60
–80
–100
–120
–40
dB
S/N+D = 58.557732
Figure 21. FFT (DAC 64 kHz Sampling—Interpolator
Bypassed)
Decoder Group Delay
The interpolator roll-off is mainly due to its sync-cubed function
characteristic, which has an inherent group delay given by the
equation.
Group Delay (Interpolator) = Order
× (L – 1)/2) × Tint
where:
Order is the interpolator order (= 3),
L is the interpolation factor (= 32) and
Tint is the interpolation sample interval
(= 1/2.048e6)
=> Group Delay (Interpolator)
= 3*(32-1)/2*(1/2.048e6)
= 22.7
s
The analog section has a group delay of approximately 25
s.
DESIGN CONSIDERATIONS
Analog Input
The analog input signal to the codec can be dc coupled, pro-
vided that the dc bias level of the input signal is the same as the
internal reference level (REFOUT). Figure 22 shows the recom-
mended differential input circuit for the AD73311’s analog
input pins (VIN). The circuit of Figure 22 implements first-
order low-pass filters with a 3 dB point at 34 kHz; these are the
only filters that must be implemented external to the AD73311
to prevent aliasing of the sampled signal. Since the codec’s ADC
uses a highly oversampled approach that transfers the bulk of
the antialiasing filtering into the digital domain, the off-chip
antialiasing filter need only be of a low order. It is recommended
that for optimum performance that the capacitors used for the
antialiasing filter be of high quality dielectric (NPO).
REFCAP
VOLTAGE
REFERENCE
0.1 F
REFOUT
TO INPUT BIAS
CIRCUITRY
100
VIN
0.047 F
VINN
VINP
AD73311
Figure 22. Example Circuit for Differential Input
(DC Coupling)
The AD73311’s on-chip 38 dB preamplifier can be enabled when
there is not enough gain in the input circuit; the preamplifier is
configured by bits IGS0–2 of CRD. The total gain must be
configured to ensure that a full-scale input signal produces a
signal level at the input to the sigma-delta modulator of the
ADC that does not exceed the maximum input range.
The dc biasing of the analog input signal is accomplished with
an on-chip voltage reference. If the input signal is not biased at
the internal reference level (via REFOUT), then it must be ac-
coupled with external coupling capacitors. CIN should be 0.1
F
or larger. The dc biasing of the input can then be accomplished
using resistors to REFOUT as in Figure 23.
REFCAP
VOLTAGE
REFERENCE
0.1 F
REFOUT
TO INPUT BIAS
CIRCUITRY
100
VIN
CIN
0.047 F
VINN
VINP
10k
AD73311
Figure 23. Example Circuit for Differential Input
(AC Coupling)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD73311LARU | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP |
| AD73311LARU-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP T/R |
| AD73311LARU-REEL7 | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP T/R |
| AD73311LARUZ | 功能描述:IC PROCESSOR FRONT END LP 20SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73311LARUZ-RL | 功能描述:IC PROCESSOR FRONT END LP 20SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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