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| 型號(hào)： | AD73311LARSZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 23/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONT END LP 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 2 |
| 功率（瓦特）： | 50mW |
| 電壓 - 電源，模擬： | 3V |
| 電壓 - 電源，數(shù)字： | 3V |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD73311LARSZ-REEL7DKR |
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AD73311A
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DAC SPECIFICATIONS (Continued)
Power Supply Rejection
–55
dB
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Group Delay
4, 5
25
s
64 kHz Input Sample Rate, Interpolator
Bypassed (CRE:5 = 1)
Output DC Offset
2, 7
–30
+20
+70
mV
PGA = 6 dB
Minimum Load Resistance, RL
2, 8
Single-Ended
150
Differential
150
Maximum Load Capacitance, CL
2, 8
Single-Ended
500
pF
Differential
100
pF
FREQUENCY RESPONSE
(ADC AND DAC)
9 Typical Output
0 Hz
0
dB
2000 Hz
–0.1
dB
4000 Hz
–0.25
dB
8000 Hz
–0.6
dB
12000 Hz
–1.4
dB
16000 Hz
–2.8
dB
20000 Hz
–4.5
dB
Channel Frequency Response Is
24000 Hz
–7.0
dB
Programmable by Means of External
28000 Hz
–9.5
dB
Digital Filtering
> 32000 Hz
< –12.5
dB
LOGIC INPUTS
VINH, Input High Voltage
VDD – 0.8
VDD
V
VINL, Input Low Voltage
0
0.8
V
IIH, Input Current
10
A
CIN, Input Capacitance
10
pF
LOGIC OUTPUT
VOH, Output High Voltage
VDD – 0.4
VDD
V
|IOUT|
≤ 100 A
VOL, Output Low Voltage
0
0.4
V
|IOUT|
≤ 100 A
Three-State Leakage Current
–10
+10
A
POWER SUPPLIES
AVDD1, AVDD2
2.7
3.3
V
DVDD
2.7
3.3
V
IDD
10
See Table I
NOTES
1Operating temperature range is as follows: –40
°C to +85°C. Therefore, T
MIN = –40
°C and T
MAX = +85
°C.
2Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).
3At input to sigma-delta modulator of ADC.
4Guaranteed by design.
5Overall group delay will be affected by the sample rate and the external digital filtering.
6The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4
× 1011)/DMCLK.
7Between VOUTP and VOUTN.
8At VOUT output.
9Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
10Test Conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
Table I. Current Summary (AVDD = DVDD = +3.3 V)
Analog
Internal Digital
External Interface
Total Current
MCLK
Conditions
Current Current
Current
(Max)
SE
ON
Comments
ADC On Only
7
3
0.5
11.5
1
YES
REFOUT Disabled
ADC and DAC On
10
5
0.5
17.5
1
YES
REFOUT Disabled
REFCAP On Only
0.75
0
1.2
0
NO
REFOUT Disabled
REFCAP and
REFOUT On Only 3.0
0
4.5
0
NO
All Sections Off
0
0.85
0
1.2
0
YES
MCLK Active Levels Equal to
0 V and DVDD
All Sections Off
0.00
0.007
0
0.04
0
NO
Digital Inputs Static and Equal
to 0 V or DVDD
The above values are in mA and are typical values unless otherwise noted.
AD73311
–3–
REV. B
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| AD73311LARU | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP |
| AD73311LARU-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP T/R |
| AD73311LARU-REEL7 | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP T/R |
| AD73311LARUZ | 功能描述:IC PROCESSOR FRONT END LP 20SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73311LARUZ-RL | 功能描述:IC PROCESSOR FRONT END LP 20SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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