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參數資料
| 型號： | AD7193BRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 44/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT SPI 4.8KHZ 28TSSOP |
| 標準包裝： | 2,500 |
| 位數： | 24 |
| 采樣率（每秒）： | 4.8k |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 1 |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 4 個差分，單極；4 個差分，雙極；8 個偽差分，單極；8 個偽差分，雙極 |
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AD7193
Data Sheet
Rev. D | Page 48 of 56
The 50 Hz/60 Hz rejection can be improved by setting the
REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and
REJ60 set to 1, the filter response shown in Figure 53 is achieved.
The output data rate is unchanged but the 50 Hz/60 Hz ± 1 Hz
rejection improves to 73 dB typically.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
25
50
75
100
125
150
FREQUENCY (Hz)
F
IL
T
E
R
GA
IN
(
d
B
)
08
36
7-
04
9
Figure 53. Sinc3 Filter Response
(FS[9:0] = 96, Chop Enabled, REJ60 = 1)
FAST SETTLING MODE (SINC4 FILTER)
In fast settling mode, the settling time is close to the inverse of
the first filter notch; therefore, the user can achieve 50 Hz and/or
60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz.
The settling time is equal to 1/output data rate. Therefore, the
conversion time is constant when converting on a single channel
or when converting on several channels. There is no added
latency when switching channels.
Enable the fast settling mode using Bit AVG1 and Bit AVG0 in
the mode register. In fast settling mode, a postfilter is included
after the sinc4 filter. The postfilter averages by 2, 8, or 16,
depending on the settings of the AVG1 and AVG0 bits.
SINC3/SINC4
POST FILTER
MODULATOR
ADC
CHOP
083
67
-05
0
Figure 54. Fast Settling Mode, Sinc4 Filter
Output Data Rate and Settling Time, Sinc4 Filter
With chop disabled, the output data rate is
fADC = fCLK/((4 + Avg 1) × 1024 × FS[9:0])
(1)
fADC is the output data rate.
fCLK is the master clock (4.92 MHz nominal).
Avg is the average.
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
If AVG1 = AVG0 = 0, the fast settling mode is not enabled.
In this case, Equation 1 is not relevant.
The settling time is equal to
tSETTLE = 1/fADC
Table 34 lists sample FS words and the corresponding output
data rates and settling times.
Table 34. Examples of Output Data Rates and the
Corresponding Settling Time (Fast Settling Mode, Sinc4)
FS[9:0]
Average
Output Data Rate (Hz)
Settling Time (ms)
96
16
2.63
380
30
16
8.4
118.75
6
16
42.1
23.75
5
16
50.53
19.79
When the analog input channel is changed, there is no additional
delay in generating valid conversions—the device functions as a
zero latency ADC.
CHANNEL
CONVERSIONS
CHANNEL A
CH A CH A CH A
CH B
CH B CH B
CHANNEL B
1/
fADC
CH B
0
83
67
-0
51
Figure 55. Fast Settling, Sinc4 Filter
When the device is converting on a single channel and a step
change occurs on the analog input, the ADC does not detect the
change and continues to output conversions. If the step change
is synchronized with the conversion, only fully settled results
are output from the ADC. However, if the step change is asyn-
chronous to the conversion process, there is one intermediate
result, which is not completely settled (see Figure 56).
ANALOG
INPUT
ADC
OUTPUT
VALID
1/
fADC
0
83
67
-0
52
Figure 56. Step Change on Analog Input, Sinc4 Filter
The output data rate is the same for chop enabled and chop
disabled in fast settling mode. However, when chop is enabled,
the settling time equals
tSETTLE = 2/fADC
Therefore, if chop is enabled, the sinc4 filter is selected, FS[9:0]
is set to 6, and averaging by 16 is enabled. The output data rate
is equal to 42.1 Hz when the master clock equals 4.92 MHz.
Therefore, the conversion time equals 1/42.10 Hz or 23.75 ms and
the settling time is equal to 47.5 ms.
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