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參數(shù)資料
| 型號(hào)： | AD7193BRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT SPI 4.8KHZ 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 4.8k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)差分，單極；4 個(gè)差分，雙極；8 個(gè)偽差分，單極；8 個(gè)偽差分，雙極 |
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Data Sheet
AD7193
Rev. D | Page 27 of 56
CONFIGURATION REGISTER
RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117
The configuration register is a 24-bit register from which data
can be read or to which data can be written. This register is
used to configure the ADC for unipolar or bipolar mode, to
enable or disable the buffer, to enable or disable the burnout
currents, to select the gain, and to select the analog input channel.
Table 22 outlines the bit designations for the configuration register.
CON0 through CON23 indicate the bit locations. CON denotes
that the bits are in the configuration register. CON23 denotes
the first bit of the data stream. The number in parentheses
indicates the power-on/reset default status of that bit.
CON23
CON22
CON21
CON20
CON19
CON18
CON17
CON16
Chop(0)
0(0)
REFSEL(0)
0(0)
Pseudo(0)
Short(0)
TEMP(0)
CON15
CON14
CON13
CON12
CON11
CON10
CON9
CON8
CH7(0)
CH6(0)
CH5(0)
CH4(0)
CH3(0)
CH2(0)
CH1(0)
CH0(1)
CON7
CON6
CON5
CON4
CON3
CON2
CON1
CON0
Burn(0)
REFDET(0)
0(0)
BUF(1)
U/B(0)
G2(1)
G1(1)
G0(1)
Table 22. Configuration Register (CON) Bit Designations
Bit Location
Bit Name
Description
CON23
Chop
Chop enable bit.
When the chop bit is cleared, chop is disabled. With chop disabled, higher conversion rates are allowed.
For an FS word of 96 decimal and the sinc4 filter selected, the conversion time is 20 ms and the settling
time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and
offset drift.
When the chop bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC
are continuously removed. However, this increases the conversion time and settling time of the ADC.
For example, when FS = 96 decimal and the sinc4 filter is selected, the conversion time with chop
enabled equals 80 ms and the settling time equals 160 ms.
CON22, CON21
0
These bits must be programmed with a Logic 0 for correct operation.
CON20
REFSEL
Reference select bits. The reference source for the ADC is selected using these bits.
REFSEL
Reference Voltage
0
External reference applied between REFIN1(+) and REFIN1().
1
External reference applied between the P1/REFIN2(+) and P0/REFIN2() pins.
CON19
0
This bit must be programmed with a Logic 0 for correct operation.
CON18
Pseudo
Pseudo differential analog inputs. The analog inputs can be configured as differential inputs or pseudo
differential analog inputs. When the pseudo bit is set to 1, the AD7193 is configured to have eight
pseudo differential analog inputs. When pseudo bit is set to 0, the AD7193 is configured to have four
differential analog inputs.
CON17 to CON8
Short, TEMP,
CH7 to CH0
Channel select bits. These bits select which channels are enabled on the AD7193 (see Table 23 and Table 24).
Several channels can be selected, and the AD7193 automatically sequences them. The conversion on
each channel requires the complete settling time. When performing calibrations or when accessing the
calibration registers, only one channel can be selected.
CON7
Burn
When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When burn = 0, the
burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and
when chop is disabled.
CON6
REFDET
Enables the reference detect function. When set, the NOREF bit in the status register indicates when the
external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference
detect circuitry operates only when the ADC is active.
CON5
0
This bit must be programmed with a Logic 0 for correct operation.
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