參數(shù)資料
型號(hào)： AD7193BRUZ-REEL
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 20/57頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT SPI 4.8KHZ 28TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 4.8k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 4 個(gè)差分，單極；4 個(gè)差分，雙極；8 個(gè)偽差分，單極；8 個(gè)偽差分，雙極
AD7193
Data Sheet
Rev. D | Page 26 of 56
MD2
MD1
MD0
Mode
1
0
Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the
calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a
calibration. The measured offset coefficient is placed in the offset register of the selected channel.
1
0
1
Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration.
RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed
in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the
selected channel. A full-scale calibration is recommended each time that the gain of a channel is changed to
minimize the full-scale error. When AVDD is less than 4.75 V, the CLK_DIV bit must be set when performing the
internal full-scale calibration.
1
0
System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as
selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and
returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured
offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is recommended
each time that the gain of a channel is changed.
1
System full-scale calibration. The user should connect the system full-scale input to the channel input pins as
selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and
returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured
full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is recommended
each time the gain of a channel is changed.
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