參數(shù)資料
型號(hào)： AD7193BRUZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 42/57頁(yè)
文件大小： 0K
描述： IC ADC 24BIT SPI 4.8KHZ 28TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 4.8k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)差分，單極；4 個(gè)差分，雙極；8 個(gè)偽差分，單極；8 個(gè)偽差分，雙極
AD7193
Data Sheet
Rev. D | Page 46 of 56
When a channel change occurs, the modulator and filter reset.
The complete settling time is required to generate the first
conversion after the channel change. Subsequent conversions on
this channel occur at 1/fADC.
CHANNEL
CONVERSIONS
CHANNEL A
CH A
CH B
CHANNEL B
1/
fADC
CH B
0
83
67
-0
41
Figure 45. Channel Change (Sinc4 Chop Enabled)
When conversions are performed on a single channel and a
step change occurs, the ADC does not detect the change in
analog input; therefore, it continues to output conversions
at the programmed output data rate. However, it is at least two
conversions later before the output data accurately reflects
the analog input. If the step change occurs while the ADC is
processing a conversion, the ADC takes three conversions after
the step change to generate a fully settled result.
1/
fADC
ANALOG
INPUT
ADC
OUTPUT
FULLY
SETTLED
0
836
7-
0
42
Figure 46. Asynchronous Step Change in Analog Input (Sinc4 Chop Enabled)
The cutoff frequency f3dB is equal to
f3dB = 0.24 × fADC
50 Hz/60 Hz Rejection (Sinc4 Chop Enabled)
When FS[9:0] is set to 96 and chopping is enabled, the output
data rate is equal to 12.5 Hz for a 4.92 MHz master clock. The
filter response shown in Figure 47 is obtained. The chopping
introduces notches at odd integer multiples of fADC/2. The notches
due to the sinc filter in addition to the notches introduced by
the chopping mean that simultaneous 50 Hz and 60 Hz rejection
is achieved for an output data rate of 12.5 Hz. The rejection at
50 Hz/60 Hz ± 1 Hz is typically 63 dB, assuming a stable
master clock.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
25
50
75
100
125
150
FREQUENCY (Hz)
F
IL
T
E
R
GA
IN
(
d
B
)
0
83
67
-04
3
Figure 47. Sinc4 Filter Response (FS[9:0] = 96, Chop Enabled)
The 50 Hz/60 Hz rejection can be improved by setting the
REJ60 bit in the mode register to 1. With FS[9:0] set to 96
and REJ60 set to 1, the filter response shown in Figure 48
is achieved. The output data rate is unchanged but the 50 Hz/
60 Hz (±1 Hz) rejection is increased to 83 dB typically.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
255075
100
125
150
FREQUENCY (Hz)
F
IL
T
E
R
GA
IN
(d
B
)
08
36
7-
0
44
Figure 48. Sinc4 Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1)
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