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參數(shù)資料
| 型號： | AD7002 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | M83723 4C 4#12 PIN RECP |
| 中文描述： | LC2MOS GSM基帶I / O端口 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 455K |
| 代理商： | AD7002 |
AD7002
–8–
REV. B
CIRCUIT DESCRIPTION
TRANSMIT SECTION
The transmit section of the AD7002 generates GMSK I and Q
waveforms in accordance with GSM recommendation 5.04.
This is accomplished by a digital GMSK modulator, followed
by 10-bit DACs for the I and Q channels and on-chip recon-
struction filters. The GMSK (Gaussian Minimum Shift Keying)
digital modulator generates I and Q signals, at 16
3
oversam-
pling, in response to the transmit data stream. The I and Q data
streams drive 10-bit DACs, which are filtered by on-chip Bessel
low-pass filters.
GUASSIAN
FILTER
INTEGRATOR
COSINE
LOOK UP
TABLE
SINE
LOOK UP
TABLE
IDATA
QDATA
10
10
DIFFERENTIAL
ENCODER
Tx DATA
GMSK PULSE SHAPING ROM
16x OVERSAMPLING
Figure 3. GMSK Functional Block Diagram
Table I. Truth Table for the Differential Encoder
Tx DATA
i
Tx DATA
i–1
Differentially Encoded Data
0
0
1
1
0
1
0
1
+1
–1
–1
+1
GMSK Modulator
Figure 3 shows the functional block diagram of the GMSK
modulator. This is implemented using control logic with a
ROM look up table, to generate I and Q data samples at
16 times the transmit data rate. The transmit data (Tx DATA)
is first differentially encoded as specified by GSM 5.04 section
2.3 (Table I). The GMSK modulator generates 10-bit I and Q
waveforms (Inphase and Quadrature), in response to the en-
coded data, which are loaded into the 10-bit I and Q transmit
DACs. The Gaussian filter, in the GMSK modulator, has an
impulse response truncated to four data bits.
When the transmit section is brought out of sleep mode
(Tx SLEEP low), the modulator is reset to a transmitting all 1s
state. When Tx SLEEP is asserted (Tx SLEEP high), the trans-
mit section powers down, with the I Tx and Q Tx outputs con-
nected to V
REF
through a nominal impedance of 80 k
.
Reconstruction Filters
The reconstruction filters smooth the DAC output signals,
providing continuous time I and Q waveforms at the output
pins. These are Bessel low-pass filters with a cutoff frequency of
approximately 300 kHz. Figure 5 shows a typical transmit filter
frequency response, while Figure 6 shows a typical plot of group
delay versus frequency. The filters are designed to have a linear
phase response in the passband and due to the reconstruction
filters being on-chip, the phase mismatch between the I and Q
transmit channels is kept to a minimum.
Transmit Section Digital Interface
Figure 4 shows the timing diagram for the transmit interface.
Tx SLEEP is sampled on the falling edge of CLK1. When
Tx SLEEP is brought low, Tx CLK becomes active after 24
master clock cycles. Tx CLK can be used to clock out the
transmit data from the ASIC or DSP on the rising edge and
Tx DATA is clocked into the AD7002 on the falling edge of
Tx CLK. When Tx SLEEP is asserted the transmit section is
immediately put into sleep mode, disabling Tx CLK and power-
ing down the transmit section.
VALID DATA
t
4
t
5
CLK1 (I)
Tx SLEEP (I)
Tx CLK (O)
Tx DATA (I)
t
7
t
12
t
6
t
11
VALID DATA
VALID DATA
t
8
t
9
t
10
t
13
NOTE: (I) = DIGITAL INPUT; (0) = DIGITAL OUTPUT
Figure 4. Transmit Section Timing Diagram
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