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參數(shù)資料
| 型號(hào)： | AD7002 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | M83723 4C 4#12 PIN RECP |
| 中文描述： | LC2MOS GSM基帶I / O端口 |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 455K |
| 代理商： | AD7002 |
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AD7002
–6–
REV. B
INPUT CLOCK TIMING
1
Limit at
T
A
= –40
8
C to +85
8
C
Parameter
Units
Description
t
1
t
2
t
3
76
30
30
ns min
ns min
ns min
CLK1, CLK2, AUX CLK Cycle Time
CLK1, CLK2, AUX CLK High Time
CLK1, CLK2, AUX CLK Low Time
TRANSMIT SECTION TIMING
Limit at
T
A
= –40
8
C to +85
8
C
Parameter
Units
Description
t
4
t
5
t
6
10
20
24 t
1
24 t
1
+ 80
48 t
1
24 t
1
24 t
1
0
100
30
30
10
0
23 t
1
10
10
ns min
ns min
ns min
ns max
ns
ns
ns
ns min
ns max
ns max
ns max
ns min
ns min
ns max
ns typ
ns typ
Tx SLEEP Hold Time
Tx SLEEP Setup Time
Tx CLK Active After CLK1 Rising Edge Following
Tx SLEEP Low
Tx CLK Cycle Time
Tx CLK High Time
Tx CLK Low Time
Propagation Delay from CLK1 to Tx CLK
t
7
t
8
t
9
t
10
t
11
t
12
t
13
Data Setup Time
Data Hold Time
Tx CLK to Tx SLEEP Asserted for Last Tx CLK Cycle
2
t
14
t
15
Digital Output Rise Time
3
Digital Output Fall Time
3
AUXILIARY DAC TIMING
Limit at
T
A
= –40
8
C to +85
8
C
Parameter
Units
Description
t
16
t
17
t
18
t
19
t
20
t
21
t
22
10
10
25
20
50
10
10
ns min
ns min
ns min
ns min
ns max
ns typ
ns typ
AUX DATA Setup Time
AUX DATA Hold Time
AUX LATCH to SCLK Falling Edge Setup Time
AUX LATCH to SCLK Falling Edge Hold Time
AUX LATCH High to AUX FLAG Valid Delay
Digital Output Rise Time
Digital Output Fall Time
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t
specifies a window, that Tx SLEEP should be asserted for the current Tx CLK to be the last prior to entering SLEEP mode.
3
Digital output rise and fall times specify the time required for the output to go between 10% and 90% of 5 V.
Specifications subject to change without notice.
(AV
DD
= +5 V
6
10%; DV
DD
= +5 V
6
10%; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted)
(AV
DD
= +5 V
6
10%; DV
DD
= +5 V
6
10%; AGND = DGND = 0 V, f
CLK1
= f
CLK2
= 13 MHz;
T
A
= T
MIN
to T
MAX
, unless otherwise noted)
CLK1, CLK2,
AUX CLK
t
1
t
2
t
3
Figure 1. Clock Timing
TO OUTPUT
PIN
+2.1V
I
OL
1.6mA
I
OH
200
μ
A
C
L
15pF
Figure 2. Load Circuit for Timing Specifications
(AV
DD
= +5 V
6
10%; DV
DD
= +5 V
6
10%; AGND = DGND = 0 V, f
AUX CLK
= 13 MHz; T
A
= T
MIN
to T
MAX
,
unless otherwise noted)
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