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參數(shù)資料
| 型號： | AD7002 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | M83723 4C 4#12 PIN RECP |
| 中文描述： | LC2MOS GSM基帶I / O端口 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 455K |
| 代理商： | AD7002 |
AD7002
–7–
REV. B
RECEIVE SECTION TIMING
1
Limit at
T
A
= –40
8
C to +85
8
C
Parameter
Units
Description
t
23
t
24
t
25
0
25
0
39 t
1
15 t
1
ns min
ns min
ns min
ns max
ns max
Rx SLEEP Hold Time After CLK1, CLK2 High
Rx SLEEP Setup Time Before CLK1, CLK2 High
Rx SYNC to Rx SLEEP Asserted
2
RATE 0
RATE 1
Rx CLK Active After CLK1 Rising Edge Following Falling
Edge of Rx SLEEP
MODE 0
MODE 1
Rx CLK Cycle Time
3
MODE 0
MODE 1
Rx CLK High Pulse Width
MODE 0
MODE 1
Rx CLK Low Pulse Width
MODE 0
MODE 1
Propagation Delay from CLK1, CLK2 High to Rx CLK High
t
26
32 t
1
+ t
2
31 t
1
+ t
2
ns
ns
t
27
t
1
2 t
1
ns
ns
t
28
25
90
ns min
ns min
t
29
25
30
10
30
20
ns min
ns min
ns min
ns max
ns min
t
30
t
31
t
32
Rx SYNC Valid Prior to Rx CLK Falling
Rx SYNC High Pulse Width
MODE 0
MODE 1
Rx SYNC Cycle Time
3
MODE 0 RATE 0
MODE 0 RATE 1
MODE 1 RATE 0
MODE 1 RATE 1
Rx DATA Valid After Rx CLK Rising Edge
MODE 0
MODE 1
MODE 0 only, Propagation Delay from Rx CLK Rising
Edge to I/
Q
Digital Output Rise Time
4
Digital Output Fall Time
4
t
1
2 t
1
ns
ns
t
33
24 t
1
12 t
1
48 t
1
24 t
1
ns
ns
ns
ns
t
34
5
t
1
+ 5
5
ns max
ns max
ns max
t
35
t
36
t
37
10
10
ns typ
ns typ
CALIBRATION AND CONTROL TIMING
Limit at
T
A
= –40
8
C to +85
8
C
Parameter
Units
Description
t
38
t
39
t
40
25
608 t
1
25
ns min
ns min
ns min
SLEEP to CAL Setup Time
CAL Pulse Width
RATE, MODE or THREE-STATE ENABLE Setup Time
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t
25
specifies a window, after Rx SYNC which marks the beginning of I data, that Rx SLEEP should be asserted for the subsequent IQ data pair to be last prior to
entering SLEEP mode.
3
See Figure 2 for test circuit.
4
Digital output rise and fall times specify the time required for the output to go between 10% and 90% of 5 V.
Specifications subject to change without notice.
(AV
DD
= +5 V
6
10%; DV
DD
= +5 V
6
10%; AGND = DGND = 0 V, f
CLK1
= f
CLK2
= 13 MHz;
T
A
= T
MIN
to T
MAX
, unless otherwise noted)
(AV
DD
= +5 V
6
10%; DV
DD
= +5 V
6
10%; AGND = DGND = 0 V, f
AUX CLK
= 13 MHz;
T
A
= T
MIN
to T
MAX
, unless otherwise noted)
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