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參數(shù)資料
| 型號： | AD7002 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | M83723 4C 4#12 PIN RECP |
| 中文描述： | LC2MOS GSM基帶I / O端口 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 455K |
| 代理商： | AD7002 |
AD7002
–15–
REV. B
PIN FUNCTION DESCRIPTIONS
PQFP Pin
Number
Mnemonic
Function
POWER SUPPLY
37
38
4, 15
5, 16
AV
DD
AGND
DV
DD
DGND
Positive power supply for analog section. This is +5 V
±
10%.
Analog ground.
Positive power supply for digital section. This is +5 V
±
10%.
Digital ground.
ANALOG SIGNAL AND REFERENCE
41
I Tx
Analog output for the I (In-Phase) channel. This output comes from a 10-bit DAC and is
filtered by a Bessel low pass filter. The 10-bit DAC is loaded with I data, which is generated
by the GMSK modulator.
Analog output for the Q (Quadrature) channel. This output comes from a 10-bit DAC and is
filtered by a Bessel low pass filter. The 10-bit DAC is loaded with Q data, which is generated
by the GMSK modulator.
Analog input for I receive channel.
Analog input for Q receive channel.
Analog output voltage from the 9-bit auxiliary DAC. This is a voltage mode DAC with a high
output impedance and hence should be buffered if used to drive moderate impedance loads.
Analog output voltage from the 10-bit auxiliary DAC. This is a voltage mode DAC with a
high output impedance and hence should be buffered if used to drive moderate impedance
loads.
Analog output voltage from the 8-bit auxiliary DAC. This is a voltage mode DAC with a high
output impedance and hence should be buffered if used to drive moderate impedance loads.
Reference output; this is 2.48 volts nominal.
39
Q Tx
44
42
34
I Rx
Q Rx
AUX DAC1
36
AUX DAC2
35
AUX DAC3
40
REFOUT
TRANSMIT INTERFACE AND CONTROL
7, 11
CLK1, CLK2
Master clock inputs for both the transmit and receive sections. CLK1 and CLK2 must be
externally hardwired together and driven from a 13 MHz TTL compatible crystal.
Clock output from the AD7002 which can be used to clock in the data for the transmit section.
Data input for the transmit section, data is clocked on the falling edge of Tx CLK.
Sleep control input for transmit section. When it is high, the transmit section goes into
standby mode and draws minimal current.
3
2
1
Tx CLK
Tx DATA
Tx SLEEP
RECEIVE INTERFACE AND CONTROL
13
MODE
Digital control input. When High (MODE 1), the I and Q outputs are on separate pins
(QDATA and IDATA). When Low (MODE 0), I and Q are on the same pin (Rx DATA).
Digital control input. This determines whether the receive section interface operates at a
word rate of 541.7 kHz or at a word rate of 270.8 kHz. When High (RATE 1), the output
word rate is 541.7 kHz. When Low (RATE 0), the output word rate is 270.8 kHz.
Rx DATA (IDATA) This is a dual function digital output. When the device is operating in MODE 0, the Rx
DATA (both I and Q) is available at this pin. When the device is operating in MODE 1, only
IDATA is available at this pin.
12
RATE
18
VOLTAGE REFERENCE
The AD7002 contains an on-chip bandgap reference that pro-
vides a low noise, temperature compensated reference to the IQ
transmit DACs and the IQ receive ADCs. The reference is also
made available on the REFOUT pin and can be used to bias
other analog circuitry in the IF section.
When both the transmit section and the receive section are in
sleep mode (Tx SLEEP and Rx SLEEP asserted), the reference
output buffer is also powered down by approximately 80%
compatible crystal.
t
17
AUX CLK (I)
AUX DATA (I)
AUX LATCH (I)
AUX FLAG (O)
DB15
DB14
DB1
DB0
t
19
t
20
t
16
NEW AUX FLAG
OLD AUX FLAG
t
18
Figure 22. Auxiliary DAC Timing Diagram
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