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參數(shù)資料
| 型號： | AD7002 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | M83723 4C 4#12 PIN RECP |
| 中文描述： | LC2MOS GSM基帶I / O端口 |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 455K |
| 代理商： | AD7002 |
AD7002
–16–
REV. B
C
P
PQFP Pin
Number
Mnemonic
Function
19
I/
Q
(QDATA)
This is a dual function digital output. When the device is operating in MODE 0, it indicates
whether IDATA or QDATA is present on Rx DATA pin. In MODE 1, QDATA is available at
this pin.
Synchronization output for framing I and Q data at the receive interface.
Output clock for the receive section interface.
This digital input controls the output three-state drivers on the receive section interface. When
it is High, the outputs are enabled. When Low, they are in high impedance.
Calibration control pin for digital filter section. When brought high, for a minimum of 608 master
clock cycles, the receive section enters a calibration cycle. Where I and Q offset registers are up-
dated, when the CAL pin is brought low again, with offset values which are subtracted out from
subsequent ADC conversions. CAL should remain Low during normal operation.
Digital control input. When high the analog modulator input is internally grounded (i.e., tied to
V
REF
). MZERO, in conjunction with CAL, allows on-chip offsets to be calibrated out. Low for
normal operation.
Power-down control inputs for receive section. When high, the receive section goes into
standby mode and draws minimal current. Rx SLEEP
1
and Rx SLEEP
2
must be externally
hardwired together for normal device operation.
20
21
22
Rx SYNC
Rx CLK
THREE-STATE
CONTROL
CAL
23
29
MZERO
27, 24
Rx SLEEP
1
,
Rx SLEEP
2
AUXILIARY INTERFACE AND CONTROL
32
AUX LATCH
31
AUX CLK
Synchronization input for the auxiliary DACs’ shift register and AUX OUT.
Clock input for the auxiliary DACs’ 16-bit shift register. AUX DATA is latched on the falling
edge of AUX CLK while AUX LATCH is low.
Data input for the AUX DACs and the AUX FLAG serial interface.
Digital output flag, this can be used as a digital control output and is controlled from the auxiliary
serial interface.
30
33
AUX DATA
AUX FLAG
TEST
8, 26
Test l, Test 2
Test pins for factory use only. These pins should be left unconnected and not used as routes for
other circuit signals.
Test pins. These must be tied to ground for normal device operation.
14, 43
Test 3, Test 4
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic Quad Flatpack Package
(S-44)
1
44
34
33
23
22
12
11
TOP VIEW
PIN 1
0.016 (0.41)
0.012 (0.30)
0.033 (0.84)
0.029 (0.74)
0.096 (2.44)
MAX
0.037 (0.94)
0.025 (0.64)
0.398 (10.11)
0.390 (9.91)
0.083 (2.11)
0.077 (1.96)
0.040 (1.02)
0.032 (0.81)
0.040 (1.02)
0.032 (0.81)
0.398 (10.11)
0.390 (9.91)
0.548 (13.925)
0.546 (13.875)
8
°
0.8
°
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