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參數(shù)資料
| 型號： | AD668AQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 12-Bit Ultrahigh Speed Multiplying D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.12 us SETTLING TIME, 12-BIT DAC, CDIP24 |
| 封裝： | 0.300 INCH, SKINNY, CERDIP-24 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 602K |
| 代理商： | AD668AQ |
AD668
REV. A
–14–
Figure 23. Settling Time Circuit
Digital Settling Time vs. V
REF
The reference amplifier loop has been compensated for optimal
settling performance at V
REF
/V
NOM
= 100%, but as Figure 24
indicates, there is relatively little degradation in settling perfor-
mance for a wide range of reference levels. Consideration of
Figures 15, 16, and 24 support that a 1/2 power solution would
see very little degradation in speed or accuracy performance.
Figure 24. Digital Settling Time vs. Reference Level
Analog Settling Time
One of the biggest challenges in measuring the settling time of a
high accuracy amplifier is producing a clean waveform with
which to drive the input. In this case, an AD568 was used to
drive the analog channel in the 1 V input mode (see Figure 13).
As indicated by Figure 25, the referred-to-output slew rate is
30 V/
μ
s for a 1 V output. This implies that a full-scale analog
input sine waves of greater than 10 MHz frequency will suffer
some slew-induced distortion. It should be noted that the
slewing limitation is in the reference amplifier, not in the DAC
output, so a 10 V buffered output voltage would slew at
300 V/
μ
s, provided the output buffer is sufficiently fast.
Figure 25. Typical Analog Settling Characteristic
Undervoltage Recovery Time
The ramifications of exceeding the specified lower limit of 10%
on the reference channel depend on the extent and duration of
the undervoltage condition. Figure 26 illustrates that, after hold-
ing the reference at 0% (REFIN = REFCOM) for 1
μ
s, the
AD668 takes 35 ns to return to 10% of full scale once the refer-
ence is returned to 100%. This is the worst case: recovery from
a completely “off” condition.
Figure 26. Undervoltage Recovery
Glitch Impulse
The AD668’s glitch at the major carry is illustrated in Figure 2.
The AD668 features a conventional DAC architecture that has
two basic glitch mechanisms: digital feedthrough and data skew.
Careful consideration of these mechanisms will help the glitch-
conscious user minimize glitch in his application.
Digital Feedthrough
As with any converter product, a high speed digital-to-analog
converter is forced to exist on the frontier between the noisy
environment of high speed digital logic and the sensitive analog
domain. The problems of this interfacing are particularly acute
when demands of high speed (greater than 10 MHz switching
times) and high precision (12 bits or more) are combined. No
amount of design effort can perfectly isolate the analog portions
of a DAC from the spectral components of a digital input signal
with a 2 ns rise time. Inevitably, once this digital signal is
brought onto the chip, some of its higher frequency components
will find their way to the sensitive analog nodes, producing a
digital feedthrough glitch. To minimize the exposure to this ef-
fect, the AD668 has intentionally omitted the on-board latches
that have been included in many slower DACs. This not only
reduces the overall level of digital activity on chip, it also avoids
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| AD668J | 12-Bit Ultrahigh Speed Multiplying D/A Converter |
| AD668K | 12-Bit Ultrahigh Speed Multiplying D/A Converter |
| AD668KQ | RES 36.0 OHM 1/8W 1% 0805 SMD |
| AD668S | 12-Bit Ultrahigh Speed Multiplying D/A Converter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD668J | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Ultrahigh Speed Multiplying D/A Converter |
| AD668JQ | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R/Current Steering 12-bit 24-Pin CDIP Tube |
| AD668K | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Ultrahigh Speed Multiplying D/A Converter |
| AD668KQ | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| AD668S | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Ultrahigh Speed Multiplying D/A Converter |
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