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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD664KP |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 23/23闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DAC 12BIT QUAD MONO 44-PLCC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Data Converter Fundamentals DAC Architectures |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 瑷�(sh猫)缃檪闁擄細 | 8µs |
| 浣嶆暩(sh霉)锛� | 12 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 骞惰伅(li谩n) |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 4 |
| 闆诲闆绘簮锛� | 闆� ± |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 525mW |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 44-LCC锛圝 褰㈠紩绶氾級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 44-PLCC锛�16.59x16.59锛� |
| 鍖呰锛� | 绠′欢 |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 4 闆诲锛屽柈妤碉紱4 闆诲锛岄洐妤� |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 125k |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�鐣�(d膩ng)鍓嶇23闋�
AD664
REV.
鈥�9鈥�
Figure 10a. Preload First Rank of a DAC
25 CTMIN to TMAX
SYMBOL
MIN (ns)
tLS
00
tLH
15
tCW
80
100
tDS
00
tDH
15
tAS
00
tAH
15
Figure 10b. Preload First Rank of a DAC Timing
This allows the user to 鈥減reload鈥� the data to a DAC and strobe
it into the output latch at some future time. The user could do
this by reproducing the sequence of signals illustrated in the
next section.
Update Second Rank of a DAC
Assuming that a new input code had previously been placed into
the first rank of the input latches, the user can update the out-
put of the DAC by simply pulling CS low while keeping LS,
MS
, TR, RD and RST high. Address data is not needed in this
case. In reality, all second ranks are being updated by this pro-
cedure, but only those which receive data different from that
already there would manifest a change. Updating the second
rank does not change the contents of the first rank.
Figure 11. Update Second Rank of a DAC
The same options that exist for individual DAC input loading
also exist for multiple DAC input loading. That is, the user can
choose to update the first and second ranks of the registers or
preload the first ranks and then update them at a future time.
Preload Multiple First Rank Registers
The first ranks of the DAC input registers may be preloaded
with new input data without disturbing the second rank data.
This is done by transferring the data into the first rank by bring-
ing CS low while LS is low. But CS must return high before LS.
This prevents the data from the first rank from getting into the
second rank. A simple second rank update cycle as shown in
Figure 11 would move the 鈥減reloaded鈥� information to the
DACs.
Figure 12. Preload First Rank Registers
Load and Update Multiple DAC Outputs
The following examples demonstrate two ways to update all
DAC outputs. The first method involves doing all data transfers
during one long CS low period. Note that in this case, shown in
Figure 13, LS returns high before CS goes high. Data hold time,
relative to an address change, is 70 ns. This updates the outputs
of all DACs simultaneously.
Figure 13. Update All DAC Outputs
The second method involves doing a CS assertion (low) and an
LS
toggle separately for each DAC. It is basically a series of
preload operations (Figure 10). In this case, illustrated in Figure
14, two LS signals are shown. One, labeled LS, goes high before
CS
returns high. This transfers the 鈥渘ew鈥� input word to the
DAC outputs sequentially. The second LS signal, labeled Alter-
nate LS, stays low until CS returns high. Using this sequence
loads the first ranks with each 鈥渘ew鈥� input word but doesn鈥檛 up-
date the DAC outputs. To then update all DAC outputs simul-
taneously would require the signals illustrated in Figure 11.
Figure 14. Load and Update Multiple DACs
SELECTING GAIN RANGE AND MODES (44-PIN
VERSIONS)
The AD664鈥檚 mode select feature allows a user to configure the
gain ranges and output modes of each of the four DACs.
On-board switches take the place of up to eight external relays
that would normally be required to accomplish this task. The
switches are programmed by the mode select word entered via
the data I/O port. The mode select word is eight-bits wide and
D
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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