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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD664KP |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 12/23闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DAC 12BIT QUAD MONO 44-PLCC |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | Data Converter Fundamentals DAC Architectures |
| 妯欐簴鍖呰锛� | 1 |
| 瑷疆鏅傞枔锛� | 8µs |
| 浣嶆暩(sh霉)锛� | 12 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 骞惰伅(li谩n) |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 4 |
| 闆诲闆绘簮锛� | 闆� ± |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 525mW |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 44-LCC锛圝 褰㈠紩绶氾級 |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 44-PLCC锛�16.59x16.59锛� |
| 鍖呰锛� | 绠′欢 |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 4 闆诲锛屽柈妤�锛�4 闆诲锛岄洐妤� |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 125k |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�鐣跺墠绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�
AD664鈥揝PECIFICATIONS
(VLL = +5 V, VCC = +15 V, VEE = 鈥�15 V, VREF = +10 V, TA = +25 C
unless otherwise noted)
REV.
鈥�2鈥�
Model
JN/JP/AD/AJ/SD
KN/KP/BD/BJ/BE/TD/TE
Min
Typ
Max
Min
Typ
Max
Units
RESOLUTION
12
*
Bits
ANALOG OUTPUT
Voltage Range
1
UNI Versions
0
VCC 鈥� 2.0
2
*
Volts
BIP Versions
VEE + 2.0
2
VCC 鈥� 2.0
2
*
Volts
Output Current
5
*
mA
Load Resistance
2
*
k
Load Capacitance
500
*
pF
Short-Circuit Current
25
40
*
mA
ACCURACY
Gain Error
鈥�7
卤3
7鈥�5
卤2
5
LSB
Unipolar Offset
鈥�2
卤1/2
2鈥�1
卤1/4
1
LSB
Bipolar Zero
3
鈥�3
卤3/4
3鈥�2
卤1/2
2
LSB
Linearity Error
4
鈥�3/4
卤1/2
3/4
鈥�1/2
卤1/4
1/2
LSB
Linearity TMIN to TMAX
鈥�1
卤3/4
1
鈥�3/4
卤1/2
3/4
LSB
Differential Linearity
鈥�3/4
3/4
鈥�1/2
1/2
LSB
Differential Linearity TMIN to TMAX
Monotonic @ All Temperatures
Gain Error Drift
Unipolar 0 V to +10 V Mode
鈥�12
卤7
12
鈥�10
卤5
10
ppm of FSR
5/
掳C
Bipolar 鈥�5 V to +5 V Mode
鈥�12
卤7
12
鈥�10
卤5
10
ppm of FSR/
掳C
Bipolar 鈥�10 V to +10 V Mode
鈥�12
卤7
12
鈥�10
卤5
10
ppm of FSR/
掳C
Unipolar Offset Drift
Unipolar 0 V to +10 V Mode
鈥�3
卤l.5
3鈥�2
卤l
2
ppm of FSR/
掳C
Bipolar Zero Drift
Bipolar 鈥�5 V to +5 V Mode
鈥�12
卤7
12
鈥�10
卤5
10
ppm of FSR/
掳C
Bipolar 鈥�10 V to +10 V Mode
鈥�12
卤7
12
鈥�10
卤5
10
ppm of FSR/
掳C
REFERENCE INPUT
Input Resistance
1.3
2. 6
*
k
Voltage Range6
VEE + 2.0
2
VCC 鈥� 2.0
2
*
Volts
POWER REOUIREMENTS
VLL
4.5
5.0
5.5
*
Volts
ILL
@ VIH, VIL = 5 V, 0 V
0.1
1
**
mA
@ VIH, VIL = 2.4 V, 0.4 V
3
6
**
mA
VCC /VEE
11.4
16.5
*
Volts
ICC
12
15
**
mA
IEE
15
19
**
mA
Total Power
400
525
*
mW
ANALOG GROUND CURRENT7
鈥�600
卤400
+600
*
A
MATCHING PERFORMANCE
Gain
8
鈥�6
卤3
6鈥�4
卤2
4
LSB
Offset
9
鈥�2
卤1/2
2鈥�1
卤1/4
1
LSB
Bipolar Zero
10
鈥�3
卤1
3鈥�2
卤1
2
LSB
Linearity
11
鈥�1.5
卤1/2
1.5
鈥�1
卤1/2
1
LSB
CROSSTALK
Analog
鈥�90
*
dB
Digital
鈥�60
*
dB
DYNAMIC PERFORMANCE (RL = 2 k, CL = 500 pF)
Settling Time to
卤1/2 LSB
Off
鈫怋its鈫扥n, GAIN = 1, V
REF = 10
8
10
*
s
Settling Time to
卤1/2 LSB
鈥�10
鈫怴
REF 鈫�10 V, GAIN = 1, Bits On
10
*
s
Glitch Impulse
500
*
nV-sec
MULTIPLYING MODE PERFORMANCE
Reference Feedthrough @ 1 kHz
鈥�75
*
dB
Reference 鈥�3 dB Bandwidth
70
*
kHz
POWER SUPPLY GAIN SENSITIVITY
11.4 V
鈫怴
CC鈫�16.5 V
卤2
5
*
ppm/%
鈥�16.5 V
鈫怴
EE鈫掆€�11.4 V
卤2
5
*
ppm/%
4.5 V
鈫怴
LL鈫�5.5 V
卤2
5
*
ppm/%
D
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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