?/DIV>
=
OS
OS
C
(6)
This simplifies into the timed period equation (see Equation 1).
COMPONENT SELECTION
Only four component values must be selected by the user. These
are input resistance R
IN
, timing capacitor C
OS
, logic resistor R2,
and integration capacitor C
INT
. The first two determine the
input voltage and full-scale frequency, while the last two are
determined by other circuit considerations.
Of the four components to be selected, R2 is the easiest to
define. As a pull-up resistor, it should be chosen to limit the
current through the output transistor to 8 mA if a TTL
maximum V
OL
of 0.4 V is desired. For example, if a 5 V logic
supply is used, R2 should be no smaller than 5 V/8 mA or
625 ? A larger value can be used if desired.
R
IN
and C
OS
are the only two parameters available to set the full-
scale frequency to accommodate the given signal range. The swing
variable that is affected by the choice of RIN and COS is nonlinearity.
The selection guides of Figure 9 and Figure 10 show this quite
graphically. In general, larger values of COS and lower full-scale
input currents (higher values of R
IN
) provide better linearity. In
Figure 10, the implications of four different choices of R
IN
are
shown. Although the selection guide is set up for a unipolar
configuration with a 0 V to 10 V input signal range, the results
can be extended to other configurations and input signal ranges.
For a full-scale frequency of 100 kHz (corresponding to 10 V
input), among the available choices RIN = 20 k& and COS = 620 pF
gives the lowest nonlinearity, 0.0038%. In addition, the highest
frequency that gives the 20 ppm minimum nonlinearity is
approximately 33 kHz (40.2 k?and 1000 pF).
For input signal spans other than 10 V, the input resistance
must be scaled proportionately. For example, if 100 k?is called
out for a 0 V to 10 V span, 10 k& would be used with a 0 V to 1 V
span, or 200 k?with a ?0 V bipolar connection.
The last component to be selected is the integration capacitor
C
INT
. In almost all cases, the best value for C
INT
can be calculated
using the equation
(
)
minimum
pF
1000
sec
/
10
4
MAX
INT
f
F
=
(7)
When the proper value for C
INT
is used, the charge balance
architecture of the AD650 provides continuous integration
of the input signal, therefore, large amounts of noise and
interference can be rejected. If the output frequency is
measured by counting pulses during a constant gate period,
the integration provides infinite normal-mode rejection for
frequencies corresponding to the gate period and its harmonics.
However, if the integrator stage becomes saturated by an
excessively large noise pulse, then the continuous integration of
the signal is interrupted, allowing the noise to appear at the output.