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參數(shù)資料
| 型號(hào)： | AD650SD |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 385K |
| 描述： | IC V-F/F-V CONV 1MHZ 14-CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 電壓至頻率和頻率至電壓 |
| 頻率 - 最大： | 1MHz |
| 全量程： | ±150ppm/°C |
| 線性： | ±0.1% |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-CDIP |
| 包裝： | 管件 |
Data Sheet
AD650
Rev. E | Page 3 of 20
SPECIFICATIONS
T = 25癈, V
S
= ?5 V, unless otherwise noted.
Table 1.
AD650J/AD650A
AD650K/AD650B
AD650S
Model
Min Typ
Max Min Typ
Max Min Typ
Max Units
DYNAMIC PERFORMANCE
Full-Scale Frequency Range
1
1
1
MHz
Nonlinearit
1
f
MAX
= 10 kHz
0.002 0.005
0.002 0.005
0.002 0.005 %
f
MAX
= 100 kHz
0.005 0.02
0.005 0.02
0.005 0.02 %
f
MAX
= 500 kHz
0.02 0.05
0.02 0.05
0.02 0.05 %
fMAX = 1 MHz
0.1
0.05 0.1
0.05 0.1 %
Full-Scale Calibration Error
2
100 kHz
?5
?5
?5
%
1 MHz
?10
?10
?10
%
vs. Supply
3
0.015
+0.015 0.015
+0.015 0.015
+0.015
% of
FSR/V
vs. Temperature
A, B, and S Grades
at 10 kHz
?5
?5
?5 ppm/?/SPAN>C
at 100 kHz
?50
?50
?00 ppm/?/SPAN>C
J and K Grades
at 10 kHz
?5
?5
ppm/癈
at 100 kHz
?50
?50
ppm/癈
BIPOLAR OFFSET CURRENT
Activated by 1.24 k?Between
Pin 4 and Pin 5
0.45 0.5
0.55 0.45 0.5
0.55 0.45 0.5
0.55 mA
DYNAMIC RESPONSE
Maximum Settling Time for
Full-Scale Step Input
1 pulse of new frequency plus 1 約 1 pulse of new frequency plus 1 約 1 pulse of new frequency plus 1 約
Overload Recovery Time
Step Input
1 pulse of new frequency plus 1 約 1 pulse of new frequency plus 1 約 1 pulse of new frequency plus 1 約
ANALOG INPUT AMPLIFIER
(V/F CONVERSION)
Current Input Range (Figure 4) 0
+0.6 0
+0.6 0
+0.6 mA
Voltage Input Range (Figure 12) 10
0
10
0
10
0
V
Differential Impedance
2 M﹟|10 pF
2 M﹟|10 pF
2 M﹟|10 pF
Common-Mode Impedance
1000 M﹟|10 pF
1000 M﹟|10 pF
1000 M﹟|10 pF
Input Bias Current
Noninverting Input
40
100
40
100
40
100 nA
Inverting Input
?
?0
?
?0
?
?0 nA
Input Offset Voltage
(Trimmable to Zero)
?
?
? mV
vs. Temperature (T
MIN
to T
MAX
)
?0
?0
?0 礦/癈
Safe Input Voltage
盫
S
盫
S
盫
S
V
COMPARATOR (F/V CONVERSION)
Logic 0 Level
VS
1 VS
1 VS
1 V
Logic 1 Level
0
+VS 0
+VS 0
+VS V
Pulse Width Range
4
0.1
(0.3 ?tOS) 0.1
(0.3 ?tOS) 0.1
(0.3 ?tOS) 祍
Input Impedance
250
250
250
k?
OPEN COLLECTOR OUTPUT
(V/F CONVERSION)
Output Voltage in Logic 0
ISINK d 8 mA, TMIN to TMAX
0.4
0.4
0.4 V
Output Leakage Current in Logic 1
100
100
100 nA
Voltage Range
5
0
36 0
36 0
36 V
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