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參數(shù)資料
| 型號： | AD650SD |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 385K |
| 描述： | IC V-F/F-V CONV 1MHZ 14-CDIP |
| 標準包裝： | 1 |
| 類型： | 電壓至頻率和頻率至電壓 |
| 頻率 - 最大： | 1MHz |
| 全量程： | ±150ppm/°C |
| 線性： | ±0.1% |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-CDIP |
| 包裝： | 管件 |
AD650
Data Sheet
Rev. E | Page 14 of 20
100k
100
10mV
ACTUAL
IDEAL
50ppm
10V
INPUT VOLTAGE
Figure 16. Exaggerated Nonlinearity at 100 kHz Full Scale
1M
1k
10mV
ACTUAL
VOLTAGETO FREQUENCY
TRANSFER RELATION
IDEAL RELATION
600ppm
10V
INPUT VOLTAGE
600ppm
Figure 17. Exaggerated Nonlinearity at 1 MHz Full Scale
1k
10
FULL SCALE FREQUENCY Hz
100
10k
100k
1M
Figure 18. PSRR vs. Full-Scale Frequency
PSRR
The power supply rejection ratio is a specification of the change
in gain of the AD650 as the power supply voltage is changed.
The PSRR is expressed in units of parts-per-million change of
the gain per percent change of the power supply (ppm/%). For
example, consider a VFC with a 10 V input applied and an
output frequency of exactly 100 kHz when the power supply
potential is ?5 V. Changing the power supply to ?2.5 V is a
5 V change out of 30 V, or 16.7%. If the output frequency changes
to 99.9 kHz, then the gain has changed 0.1% or 1000 ppm. The
PSRR is 1000 ppm divided by 16.7%, which equals 60 ppm/%.
The PSRR of the AD650 is a function of the full-scale operating
frequency. At low full-scale frequencies the PSRR is determined
by the stability of the reference circuits in the device and can be
very effective. At higher frequencies, there are dynamic errors
that become more important than the static reference signals,
and consequently the PSRR is not quite as effective. The values
of PSRR are typically 0 ?20 ppm/% at 10 kHz full-scale frequency
(RIN = 40 k? COS = 3300 pF). At 100 kHz (RIN = 40 k? COS =
330 pF) the PSRR is typically +80 ?40 ppm/%, and at 1 MHz
(RIN = 16.9 k? COS = 51 pF) the PSRR is +350 ?50 ppm/%.
This information is summarized graphically in Figure 18.
OTHER CIRCUIT CONSIDERATIONS
The input amplifier connected to Pin 1, Pin 2, and Pin 3 is not a
standard operational amplifier. Rather, the design has been
optimized for simplicity and high speed. The single largest
difference between this amplifier and a normal op amp is the lack
of an integrator (or level shift) stage. Consequently, the voltage on
the output (Pin 1) must always be more positive than 2 V below the
inputs (Pin 2 and Pin 3). For example, in the F-to-V conversion
mode (Figure 13) the noninverting input of the op amp (Pin 2)
is grounded, which means that the output (Pin 1) is not able to
go below 2 V. Normal operation of the circuit shown in Figure 13
never calls for a negative voltage at the output, but users can
imagine an arrangement calling for a bipolar output voltage (for
example, ?0 V) by connecting an extra resistor from Pin 3 to a
positive voltage. However, this does not work.
Care should be taken under conditions where a high positive
input voltage exists at or before power up. These situations can
cause a latch up at the integrator output (Pin 1). This is a
nondestructive latch and, as such, normal operation can be
restored by cycling the power supply. Latch up can be prevented
by connecting two diodes (for example, 1N914 or 1N4148) as
shown in Figure 11, thereby preventing Pin 1 from swinging
below Pin 2.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD650SD/883B | 功能描述:電壓頻率轉(zhuǎn)換及頻率電壓轉(zhuǎn)換 IC - V/F CONVERTER IC RoHS:否 制造商:Texas Instruments 全標度頻率:4000 KHz 線性誤差:+/- 1 % FSR 電源電壓-最大: 電源電壓-最小: 最大工作溫度:+ 85 C 最小工作溫度:- 25 C 安裝風格:Through Hole 封裝 / 箱體:PDIP-14 封裝:Tube |
| AD650SD-883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:Voltage-to-Frequency and Frequency-to-Voltage Converter |
| AD650TYHHLBOX | 制造商:Advanced Micro Devices 功能描述:AMD A-SERIES APU A8-6500T X4 3100MHZ 4MB FM2 45W PIB - Boxed Product (Development Kits) |
| AD651AQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter |
| AD651SQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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