參數(shù)資料
型號(hào)： AD650SD
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 385K
描述： IC V-F/F-V CONV 1MHZ 14-CDIP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 電壓至頻率和頻率至電壓
頻率 - 最大： 1MHz
全量程： ±150ppm/°C
線性： ±0.1%
安裝類(lèi)型： 通孔
封裝/外殼： 14-CDIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 14-CDIP
包裝： 管件
Data Sheet
AD650
 
Rev. E | Page 7 of 20
CIRCUIT OPERATION
UNIPOLAR CONFIGURATION
The AD650 is a charge balance voltage-to-frequency converter.
In the connection diagram shown in Figure 4, or the block
diagram of Figure 5, the input signal is converted into an
equivalent current by the input resistance R
IN
. This current is
exactly balanced by an internal feedback current delivered in
short, timed bursts from the switched 1 mA internal current
source. These bursts of current can be thought of as precisely
defined packets of charge. The required number of charge
packets, each producing one pulse of the output transistor,
depends upon the amplitude of the input signal. Because the
number of charge packets delivered per unit time is dependent
on the input signal amplitude, a linear voltage-to-frequency
transformation is accomplished. The frequency output is
furnished via an open collector transistor.
A more rigorous analysis demonstrates how the charge balance
voltage-to-frequency conversion takes place.
A block diagram of the device arranged as a V-to-F converter is
shown in Figure 5. The unit is comprised of an input integrator,
a current source and steering switch, a comparator, and a one
shot. When the output of the one shot is low, the current
steering switch S
1
 diverts all the current to the output of the op
amp; this is called the integration period. When the one shot
has been triggered and its output is high, the switch S1 diverts
all the current to the summing junction of the op amp; this is
called the reset period. The two different states are shown in
Figure 6 and Figure 7 along with the various branch currents. It
should be noted that the output current from the op amp is the
same for either state, thus minimizing transients.
 
OP
AMP
COMP
IN
FREQ
OUT
OUT
ONE
SHOT
8
9
10
11
12
13
7
15V
0.1礔
C
OS
6
4
2
1
14
INPUT
OFFSET
TRIM
0.6V
AD650
V
S
V
S
1mA
S1
5
F
OUT
V
LOGIC
+15V
V
IN
R3  R1
R
IN
3
DIGITAL
GROUND
ANALOG
GROUND
1礔
250k&
20k&
R2
0.1礔
C
INT
 
Figure 4. Connection Diagram for V/F Conversion, Positive Input Voltage
V
IN
V
S
S1
1mA ?20%
AD650
+

R
IN
I
IN
C
INT
INTEGRATOR
0.6V
COMPARATOR
FREQUENCY
OUTPUT
ONE
SHOT
C
OS
t
t
OS
 
Figure 5. Block Diagram
V
IN
V
S
S1
1mA
R
IN
I
IN
C
INT
1mA  I
IN
1mA
 
Figure 6. Reset Mode
V
IN
V
S
S1
1mA
R
IN
I
IN
C
INT
1mA  I
IN
I
IN
1mA
 
Figure 7. Integrate Mode
RESET
INTEGRATE
0.6
V
t
OS
T
1
t
 
Figure 8. Voltage Across C
INT
 
 
 
 
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