參數(shù)資料
型號: AD607
廠商: Analog Devices, Inc.
英文描述: Low Power Mixer/AGC/RSSI 3 V Receiver IF Subsystem(低功耗混合器/AGC/RSSI 3V接收器IF子系統(tǒng))
中文描述: 低功耗混合機(jī)/自動增益控制/ RSSI的3 V接收機(jī)中頻子系統(tǒng)(低功耗混合器/自動增益控制/ RSSI的3V的接收器中頻子系統(tǒng))
文件頁數(shù): 21/24頁
文件大?。?/td> 510K
代理商: AD607
AD607
REV. 0
–21–
The board provides SMA connectors for the RF and LO port
inputs, the demodulated I and Q outputs, the manual gain con-
trol (MGC) input, the PLL input, and the power-up input. In
addition, the IF output is also available at an SMA connector;
this may be connected to the PLL input for carrier recovery to
realize synchronous AM and FM detection via the I and Q de-
modulators, respectively. Table III lists the AD607 Evaluation
Board’s I/O Connectors and their functions.
Table III. AD607 Evaluation Board Input and Output Connections
Reference
Designation
Connector
Type
Approximate
Signal Level
Description
Coupling
Comments
J1
SMA
Frequency
Detector Input
DC
±
400 mV
This pin needs to be biased at VMID
and ac coupled when driven by an
external signal generator.
J2
SMA
Power Up
DC
CMOS Logic
Level Input
–16 dBm
(
±
50 mV)
–15 dBm max
(
±
54 mV)
0.4 V to 2.0 V
(3 V Supply)
(GREF = VMID)
Tied to Positive Supply by Jumper J10.
J3
SMA
LO Input
AC
Input is terminated in 50
.
J4
SMA
RF Input
AC
Input is terminated in 50
.
J5
SMA
MGC Input
or
RSSI Output
DC
Jumper is set for Manual Gain Control
Input; See Table I for Control Voltage
Values.
J6
SMA
IF Output
AC
NA
This signal level depends on the
AD607’s gain setting.
This signal level depends on the
AD607’s gain setting.
This signal level depends on the
AD607’s gain setting.
Sets gain-control Scale Factor (SF);
SF = 75/VMID in dB/V, where
VMID = VPOS/2.
Remove to test Power Up/Down.
J7
SMA
Q Output
AC
NA
J8
SMA
I Output
AC
NA
J9
Jumper
Ties GREF
to VMID
NA
NA
J10
Jumper
Ties Power-Up
to Positive
Supply
Power Supply
Positive Input
(VPS1, VPS2)
Power Supply
Return (GND)
NA
NA
T1
Terminal Pin
DC
DC
2.7 V to 5.5 V
Draws 8.5 mA at
midgain connection.
T2
Terminal Pin
DC
0 V
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