參數(shù)資料
型號： AD607
廠商： Analog Devices, Inc.
英文描述： Low Power Mixer/AGC/RSSI 3 V Receiver IF Subsystem(低功耗混合器/AGC/RSSI 3V接收器IF子系統(tǒng))
中文描述： 低功耗混合機(jī)/自動(dòng)增益控制/ RSSI的3 V接收機(jī)中頻子系統(tǒng)（低功耗混合器/自動(dòng)增益控制/ RSSI的3V的接收器中頻子系統(tǒng)）
文件頁數(shù)： 2/24頁
文件大?。?/td> 510K
代理商： AD607
AD607–SPECIFICATIONS
Model
REV. 0
–2–
(@ T
A
= + 25
°
C, Supply = 3.0 V, IF = 10.7 MHz, unless otherwise noted)
AD607ARS
Min
Conditions
Typ
Max
Units
DYNAMIC PERFORMANCE
MIXER
Maximum RF and LO Frequency Range
Maximum Mixer Input Voltage
Input 1 dB Compression Point
Input Third-Order Intercept
Noise Figure
For Conversion Gain > 20 dB
For Linear Operation; Between RFHI and RFLO
RF Input Terminated in 50
RF Input Terminated in 50
Matched Input, Max Gain, f = 83 MHz, IF = 10.7 MHz
Matched Input, Max Gain, f = 144 MHz, IF = 10.7 MHz
Z
IF
= 165
, at Input Compression
–3 dB, Z
IF
= 165
Mixer LO Input Terminated in 50
LOIP to VMID
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
500
±
54
–15
–5
14
12
±
1.3
45
–16
1
30
20
40
70
MHz
mV
dBm
dBm
dB
dB
V
MHz
dBm
k
dB
dB
dB
dB
Maximum Output Voltage at MXOP
Mixer Output Bandwidth at MXOP
LO Drive Level
LO Input Impedance
Isolation, RF to IF
Isolation, LO to IF
Isolation, LO to RF
Isolation, IF to RF
IF
AMPLIFIERS
Noise Figure
Input 1 dB Compression Point
Output Third-Order Intercept
Maximum IF Output Voltage at IFOP
Output Resistance at IFOP
Bandwidth
GAIN CONTROL
Gain Control Range
Gain Scaling
Max Gain, f = 10.7 MHz
IF = 10.7 MHz
IF = 10.7 MHz
Z
IF
= 600
From IFOP to VMID
–3 dB at IFOP, Max Gain
(See Figures 43 and 44)
Mixer + IF Section, GREF to 1.5 V
GREF to 1.5 V
GREF to General Reference Voltage V
R
GREF to 1.5 V, 80 dB Span
17
–15
+18
±
560
15
45
dB
dBm
dBm
mV
MHz
90
20
75/V
R
±
1
5
1
1
dB
mV/dB
dB/V
dB
μ
A
μ
A
M
Gain Scaling Accuracy
Bias Current at GAIN/RSSI
Bias Current at GREF
Input Resistance at GAIN, GREF
I AND Q DEMODULATORS
Required DC Bias at DMIP
Input Resistance at DMIP
Input Bias Current at DMIP
Maximum Input Voltage
VPOS/2
50
2
±
150
±
75
±
0.2
–1.2
–100
18
±
1.23
10
1.5
V dc
k
μ
A
mV
mV
dB
Degrees
dBc/Hz
dB
V
mV
MHz
From DMIP to VMID
IF > 3 MHz
IF
≤
3 MHz
IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz
IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz
IF = 10.7 MHz, F = 10 kHz
Sine Wave Input, Baseband Output
R
L
≥
20 k
Measured from I
, Q
to VMID
Sine Wave Input, Baseband Output
Amplitude Balance
Quadrature Error
Phase Noise in Degrees
Demodulation Gain
Maximum Output Voltage
Output Offset Voltage
Output Bandwidth
PLL
Required DC Bias at FDIN
Input Resistance at FDIN
Input Bias Current at FDIN
Frequency Range
Required Input Drive Level
Acquisition Time to
±
3
°
VPOS/2
50
200
0.4 to 12
400
16.5
V dc
k
nA
MHz
mV
μ
s
From FDIN to VMID
Sine Wave Input at Pin 1
IF = 10.7 MHz
POWER-DOWN INTERFACE
Logical Threshold
Input Current for Logical High
Turn-On Response Time
Standby Current
POWER SUPPLY
Supply Range
Supply Current
OPERATING TEMPERATURE
T
MIN
to T
MAX
For Power Up on Logical High
2
75
16.5
550
V dc
μ
A
μ
s
μ
A
To PLL Locked
2.7
5.5
V
mA
Midgain, IF = 10.7 MHz
8.5
Operation to 2.7 V Minimum Supply Voltage
Operation to 4.5 V Minimum Supply Voltage
–25
–40
+85
+85
°
C
°
C
Specifications subject to change without notice.
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