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參數(shù)資料
| 型號： | AD607 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power Mixer/AGC/RSSI 3 V Receiver IF Subsystem(低功耗混合器/AGC/RSSI 3V接收器IF子系統(tǒng)) |
| 中文描述： | 低功耗混合機/自動增益控制/ RSSI的3 V接收機中頻子系統(tǒng)（低功耗混合器/自動增益控制/ RSSI的3V的接收器中頻子系統(tǒng)） |
| 文件頁數(shù)： | 14/24頁 |
| 文件大小： | 510K |
| 代理商： | AD607 |
REV. 0
–14–
AD607
Table I. AD607 Filter Termination Resistor Values for
Common IFs
Filter
Impedance
Filter Termination Resistor
Values
1
for 24 dB of Mixer Gain
IF
R1
174
174
215
330
R2
1330
1330
787
0
R3
1500
1500
1000
330
450 kHz
455 kHz
6.5 MHz
10.7 MHz
1500
1500
1000
330
NOTES
1
Resistor values were calculated such that R1+ R2 = Z
FILTER
and
R1
i
(R2 + Z
FILTER
) = 165
.
The maximum permissible signal level at MXOP is determined
by both voltage and current limitations. Using a 3 V supply and
VMID at 1.5 V, the maximum swing is about
±
1.3 V. To attain
a voltage swing of
±
1 V in the standard IF filter load of 165
load requires a peak drive current of about
±
6 mA, which is well
within the linear capability of the mixer. However, these upper
limits for voltage and current should not be confused with issues
related to the mixer gain, already discussed. In an operational
system, the AGC voltage will determine the mixer gain, and
hence the signal level at the IF input pin IFHI; it will always be
less than
±
56 mV (–15 dBm into 50
), which is the limit of
the IF amplifier’s linear range.
IF Amplifier
Most of the gain in the AD607 arises in the IF amplifier strip,
which comprises four stages. The first three are fully differential
and each has a gain span of 25 dB for the nominal AGC voltage
range. Thus, in conjunction with the mixer’s variable gain, the
total gain exceeds 90 dB. The final IF stage has a fixed gain of
20 dB, and it also provides differential to single-ended conversion.
The IF input is differential, at IFHI (noninverting relative to the
output IFOP) and IFLO (inverting). Figure 36 shows a simpli-
fied schematic of the IF interface. The offset voltage of this
stage would cause a large dc output error at high gain, so it is
nulled by a low-pass feedback path from the IF output, also
shown in Figure 25. Unlike the mixer output, the signal at IFOP
is a low-impedance single-sided voltage, centered at V
P
/2 by the
DC feedback loop. It may be loaded by a resistance as low as
50
which will normally be connected to VMID.
10k
10k
VMID
AD607
IFHI
IFLO
OFFSET FEEDBACK
LOOP
IFOP
Figure 36. Simplified Schematic of the IF Interface
The mixer’s RF input port is differential, that is, pin RFLO is
functionally identical to RFHI, and these nodes are internally
biased; we will generally assume that RFLO is decoupled to ac
ground. The RF port can be modeled as a parallel RC circuit as
shown in Figure 34.
R
IN
C
IN
C2
C1
C3
L1
RFHI
RFLO
AD607
C1, C2, L1: OPTIONAL MATCHING CIRCUIT
C3: COUPLES RFLO TO AC GROUND
Figure 34. Mixer Port Modeled as a Parallel RC Network;
an Optional Matching Network Is also Shown
The local oscillator (LO) input is internally biased at V
P
/2 via a
nominal 1000
resistor internally connected from pin LOIP to
VMID. The LO interface includes a preamplifier which mini-
mizes the drive requirements, thus simplifying the oscillator de-
sign and reducing LO leakage from the RF port. Internally, this
single-sided input is actually differential; the noninverting input
is referenced to pin VMID. The LO requires a single-sided drive
of
±
50 mV, or –16 dBm in a 50
system.
The mixer’s output passes through both a low-pass filter and a
buffer, which provides an internal differential to single-ended
signal conversion with a bandwidth of approximately 45 MHz.
Its output at pin MXOP is in the form of a single-ended current.
This approach eliminates the 6 dB voltage loss of the usual se-
ries termination by replacing it with shunt terminations at the
both the input and the output of the filter. The nominal conver-
sion gain is specified for operation into a total IF bandpass filter
(BPF) load of 165
, that is, a 330
filter, doubly-terminated
as shown in Figure 33. Note that these loads are connected to
bias point VMID, which is always at the midpoint of the supply
(that is, V
P
/2).
The conversion gain is measured between the mixer input and
the input of this filter, and varies between 1.5 dB and 26.5 dB
for a 165
load impedance. Using filters of higher impedance,
the conversion gain can always be maintained at its specified
value or made even higher; for filters of lower impedance, of say
Z
O
, the conversion gain will be lowered by 10 log
10
(165/Z
O
).
Thus, the use of a 50
filter will result in a conversion gain that
is 5.2 dB lower. Figure 35 shows filter matching networks and
Table I lists resistor values.
IFLO
BPF
MXOP
VMID
IFHI
10
11
8
9
1nF
100nF
R3
100nF
R1
R2
Figure 35. Suggested IF Filter Matching Network. The
Values of R1 and R2 Are Selected to Keep the Impedance
at Pin MXOP at 165
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| AD607ARS | 功能描述:射頻混合器 LINEAR IF SUBSYSTEM RoHS:否 制造商:NXP Semiconductors 頻率范圍: 轉換損失——最大: 工作電源電壓:6 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| AD607ARS-REEL | 功能描述:IC RCVR IF SUBSYSTEM 3V 20-SSOP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD607ARSZ | 功能描述:IC LIN RCVR IF SUBSYS LP 20-SSOP RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD607ARSZ | 制造商:Analog Devices 功能描述:IF Subsystem |
| AD607ARSZ-REEL | 功能描述:IC RECEIVER IF SUBSYS LP 20SSOP RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
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