參數(shù)資料
型號(hào)： AD5744
廠商： Analog Devices, Inc.
英文描述： Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
中文描述： 完整，四路，14/16-Bit，高精度，串行輸入，雙極性電壓輸出DAC
文件頁(yè)數(shù)： 25/27頁(yè)
文件大?。?/td> 243K
代理商： AD5744
Preliminary Technical Data
(PC7) is taken low and data is transmitted MSB first. Data
appearing on the MOSI output is valid on the falling edge of
SCK. Eight falling clock edges occur in the transmit cycle, so, in
order to load the required 24-bit word, PC7 is not brought high
until the third 8-bit word has been transferred to the DAC’s
input shift register.
Rev. PrA 15-Nov-04| Page 25 of 27
AD5744/64*
SCLK
SDIN
SYNC
MOSI
SCLK
PC7
MC68HC11*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. AD5744/64 to MC68HC11 Interface
LDAC is controlled by the PC6 port output. The DAC can be
updated after each 3-byte transfer by bringing LDAC low. This
example does not show other serial lines for the DAC. If CLR
were used, it could be controlled by port output PC5, for
example.
AD5744/64 to 8051 Interface
The AD5744/64 requires a clock synchronized to the serial
data. For this reason, the 8051 must be operated in Mode 0. In
this mode, serial data enters and exits through RxD, and a shift
clock is output on TxD.
P3.3 and P3.4 are bit programmable pins on the serial port and
are used to drive SYNC and LDAC, respectively.
The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user must ensure that the data in the SBUF
register is arranged correctly, because the DAC expects MSB
first. When data is to be transmitted to the DAC, P3.3 is taken
low. Data on RxD is clocked out of the microcontroller on the
rising edge of TxD and is valid on the falling edge. As a result,
no glue logic is required between this DAC and the
microcontroller interface.
The 8051 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Because the DAC
expects a 24-bit word, SYNC (P3.3) must be left low after the
first eight bits are transferred. After the third byte has been
transferred, the P3.3 line is taken high. The DAC may be
updated using LDAC via P3.4 of the 8051.
AD5744/64 to ADSP2101/ADSP2103 Interface
An interface between the AD5744/64 and the ADSP2101/
ADSP2103 is shown in Figure 14. The ADSP2101/ADSP2103
should be set up to operate in the SPORT transmit alternate
framing mode. The ADSP2101/ADSP2103 are programmed
SDO
MISO
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, and
24-bit word length.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
output is updated using the LDAC pin via the DSP.
Alternatively, the LDAC input could be tied permanently low,
and then the update takes place automatically when TFS is
taken high.
AD5744/64*
SCLK
SDIN
SYNC
DT
SCLK
RFS
ADSP2101/
ADSP2103*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. AD5744/64 to ADSP2101/ADSP2103 Interface
AD5744/64 to PIC16C6x/7x Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit set to 0. This is done
by writing to the synchronous serial port control register
(SSPCON). See the
PIC16/17 Microcontroller User Manual
. In
this example, I/O port RA1 is being used to pulse SYNC and
enable the serial port of the AD5744/64. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive write operations are
needed. Figure 15 shows the connection diagram.
SDO
DR
TFS
LDAC
FO
AD5744/64*
SCLK
SDIN
SYNC
SDO/RC5
SCLK/RC3
RA1
PIC16C6x/7x*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 15. AD5744/64 to PIC16C6x/7x Interface
SDO
SDI/RC4
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