參數(shù)資料
型號(hào)： AD5744
廠商： Analog Devices, Inc.
英文描述： Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
中文描述： 完整，四路，14/16-Bit，高精度，串行輸入，雙極性電壓輸出DAC
文件頁(yè)數(shù)： 20/27頁(yè)
文件大?。?/td> 243K
代理商： AD5744
Preliminary Technical Data
Rev. PrA 15-Nov-04| Page 20 of 27
Table 11. Explanation of Function Register Options
NOP
No operation instruction used in readback operations.
Local-Ground-
Offset Adjust
Cleared by the user to disable local-ground-offset adjust function (default).
D0 / D1
Direction
Cleared by the user to enable D0/D1 as inputs (default). Have weak internal pull-ups.
D0 / D1 Value
I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when
configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When
enabled as inputs, these bits are don’t cares during a write operation.
SDO Disable
Set by the user to disable the SDO output.
Cleared by the user to enable the SDO output (default).
CLR
Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary
mode.
LOAD
Addressing this function updates the DAC registers and consequently the analog outputs.
DATA REGISTER
The Data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC Channel the Data
transfer is to take place (Refer to Table 9). The data bits are in positions D15 to D0 for the AD5764 as shown in Table 12 and D13 to D0
for the AD5744 as shown in Table 13.
Set by the user to enable local-ground-offset adjust function.
Set by the user to enable D0/D1 as outputs.
Table 12. Programming the AD5764 Data Register
REG2
0
Table 13. Programming the AD5744 Data Register
REG1
1
REG0
0
A2
DAC Address
A1
A0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
16 Bit DAC Data
REG2
0
COARSE GAIN REGISTER
The Coarse Gain Register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC Channel the
Data transfer is to take place (Refer to Table 9). The Coarse Gain Register is a 2-bit register and allows the user to select the output range
of each DAC as shown in Table 15.
REG1
1
REG0
0
A2
DAC Address
A1
A0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
X
DB0
X
14 Bit DAC Data
Table 14. Programming the Coarse Gain Register
REG2
REG1
REG0
0
1
1
A2
DAC Address
A1
A0
DB15 …. DB2
Don’t Care
DB1
CG1
DB0
CG0
Table 15. Output Range Selection
Output Range
CG1
CG0
± 10 V
± 10.25 V
± 10.5 V
0
0
1
0
1
0
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