參數(shù)資料
型號： AD5744
廠商： Analog Devices, Inc.
英文描述： Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
中文描述： 完整，四路，14/16-Bit，高精度，串行輸入，雙極性電壓輸出DAC
文件頁數(shù)： 18/27頁
文件大?。?/td> 243K
代理商： AD5744
Preliminary Technical Data
Rev. PrA 15-Nov-04| Page 18 of 27
V
OUT
DAC
REGISTER
INTERFACE
LOGIC
OUTPUT
I/V AMPLIFIER
LDAC
SDO
SDIN
16-BIT
DAC
V
REFIN
SYNC
INPUT
REGISTER
SCLK
Figure 9. Simplified Serial Interface showing input loading
circuitry for one DAC Channel
TRANSFER FUNCTION
Table 6 and Table 7 Show the ideal input code to output voltage
relationship for the AD5744/64 for both Offset binary and twos
complement data coding.
Table 6. Ideal output voltage to input code relationship for the
AD5764
Digital Input
Offset Binary Data Coding
MSB
1111
1111
1111
1000
0000
0000
1000
0000
0000
0111
1111
1111
0000
0000
0000
Twos Complement Data Coding
MSB
0111
1111
1111
0000
0000
0000
0000
0000
0000
1111
1111
1111
1000
0000
0000
Analog Output
V
OUT
+2 V
REF
x (32767/32768)
+2 V
REF
x (1/32768)
LSB
1111
0001
0000
1111
0000
0 V
-2 V
REF
x (1/32768)
-2 V
REF
x (32767/32768)
LSB
V
OUT
1111
0001
0000
1111
0000
+2 V
REF
x (32767/32768)
+2 V
REF
x (1/32768)
0 V
-2 V
REF
x (1/32768)
-2 V
REF
x (32767/32768)
Table 7. Ideal output voltage to input Code relationship for the
AD5744
Digital Input
Offset Binary Data Coding
MSB
11
1111
1111
10
0000
0000
10
0000
0000
01
1111
1111
00
0000
0000
Twos Complement Data Coding
MSB
01
1111
1111
00
0000
0000
00
0000
0000
11
1111
1111
10
0000
0000
Analog Output
V
OUT
+2 V
REF
x (8192/8192)
+2 V
REF
x (1/8192)
LSB
1111
0001
0000
1111
0000
0 V
-2 V
REF
x (1/8192)
-2 V
REF
x (8192/8192)
LSB
V
OUT
1111
0001
0000
1111
0000
+2 V
REF
x (8192/8192)
+2 V
REF
x (1/8192)
0 V
-2 V
REF
x (1/8192)
-2 V
REF
x (8192/8192)
The output voltage expression for the AD5764 is given by:
×
+
×
=
65536
4
2
D
V
V
V
REFIN
REFIN
OUT
The output voltage expression for the AD5744 is given by:
×
+
×
=
16384
4
2
D
V
V
V
REFIN
REFIN
OUT
where:
D is the decimal equivalent of the code loaded to the DAC.
V
REFIN
is the reference voltage applied at the REFIN pin.
ASYNCHRONOUS CLEAR (CLR)
CLR is an active low, level sensitive clear that allows the outputs
to be cleared to either 0 V (Offset binary coding) or negative
full scale (twos complement coding). It is necessary to maintain
CLR low for a minimum amount of time (refer to Figure 3) for
the operation to complete. When the CLR signal is returned
high, the output remains at the cleared value until a new value is
programmed. The CLR signal has priority over LDAC and
SYNC. A clear can also be initiated through software by writing
the command 0x04XXXX to the AD5744/64.
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