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參數資料
| 型號： | AD5381BSTZ-3-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 27/40頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT 40CH 3V 100-LQFP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產品變化通告： | AD5381,3 Redesign Change 24/Oct/2011 |
| 設計資源： | 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5381 (CN0010) AD5381 Channel Monitor Function (CN0013) |
| 標準包裝： | 1 |
| 設置時間： | 6µs |
| 位數： | 12 |
| 數據接口： | 串行，并聯(lián) |
| 轉換器數目： | 40 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 80mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 標準包裝 |
| 輸出數目和類型： | 40 電壓，單極 |
| 采樣率（每秒）： | 167k |
| 其它名稱： | AD5381BSTZ-3-REELDKR |
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Data Sheet
AD5381
Rev. D | Page 33 of 40
APPLICATION INFORMATION
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the ratedperformance. The printed circuit board on
which the AD5381 is mounted should be designed so that the
analog and digital sections are separatedand confined to
certain areas of the board. If the AD5381 is in a system where
multiple devices requirean AGND-to-DGNDconnection, the
connection should be made at onepoint only, a star ground
point established as close to the device as possible.
For supplies with multiple pins (AVDD, DVDD), thesepins
should be tied together. TheAD5381 should haveample supply
bypassing of 10 F in parallel with 0.1 F on each supply,
located as close to the package as possibleand ideally right
up against the device. The 10 F capacitors are the tantalum
bead type. The 0.1 F capacitor should havelow effective series
resistance (ESR)and effective series inductance (ESI), like the
common ceramictypes that providea low impedance path to
ground at high frequencies, to handletransient currents dueto
internal logic switching.
The power supplylines of the AD5381 should use as largea
trace as possible to providelow impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground
to avoid radiating noise to other partsof the board, andshould
never be run near the reference inputs.A ground line routed
between the D
IN and SCLK lines will help reduce crosstalk
between them(this is not required on a multilayerboard
because therewill be a separate ground plane, butseparat-
ing the lines will help). It is essential to minimize noise on
the REFOUT/REFIN line.
Avoid crossover of digital and analog signals. Traceson
opposite sides of the board should run at right angles to
each other. This reduces the effects of feedthrough through
the board. A micro-strip technique is by far the best, but is
not always possible with a double-sided board. In this tech-
nique, the component side of the boardis dedicated to the
ground plane while signal traces are placed on the solder side.
TYPICAL CONFIGURATIONCIRCUIT
Figure 39 shows a typical configuration for the AD5381-5
when configured for use with an external reference. In the
circuit shown, all AGND, SIGNAL_GND, and DAC_GND pins
are tied together to a common AGND. AGNDand DGNDare
connected togetherat the AD5381 device. On power-up, the
AD5381 defaults to external reference operation. All AVDD
lines are connected together and driven from the same5 V
source. It is recommended to decoupleclose to the device
with a 0.1 F ceramicand a 10 F tantalum capacitor. In this
application, the referencefor the AD5381-5 is provided
externally from eitheran ADR421 or ADR431 2.5 V reference.
Suitable external references for theAD5381-3 include the
ADR280 1.2 V reference. The reference should be decoupledat
the REFOUT/REFIN pin of the device with a 0.1 F capacitor.
03732-039
ADR431/
ADR421
AD5381-5
AVDD
DVDD
SIGNAL_GND
DAC_GND
DGND
VOUT39
VOUT0
AGND
REFOUT/REFIN
REFGND
0.1
F
10
F
0.1
F
0.1
F
AVDD
DVDD
Figure 39. Typical Configuration with External Reference
Figure 40 shows a typical configuration when using the internal
reference. On power-up, the AD5381 defaults to an external
reference; therefore, the internal reference needs to be config-
ured and turned on via a write to the AD5381 control register.
Control Register Bit CR10 allows the user to choosethe
referencevalue; Bit CR8 is used to select the internal reference.
It is recommended to use the 2.5 V reference when AVDD=
5 V, and the 1.25 V reference when AVDD= 3 V.
03732-040
AD5381
AVDD
DVDD
SIGNAL_GND
DAC_GND
DGND
VOUT39
VOUT0
AGND
REFOUT/REFIN
REFGND
0.1
F
10
F
0.1
F
0.1
F
AVDD
DVDD
Figure 40. Typical Configuration with Internal Reference
Digital connections have been omitted forclarity. The AD5381
contains an internal power-on reset circuit with a 10 ms brown-
out time. If the power supply ramp rate exceeds10 ms, the user
should reset the AD5381 as part of the initialization process to
ensure the calibration datais loaded correctly into the device.
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相關代理商/技術參數 |
參數描述 |
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| AD5381BSTZ-5 | 功能描述:IC DAC 12BIT 40CH 5V 100-LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數:8 數據接口:串行 轉換器數目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5381BSTZ-5-REEL | 功能描述:IC DAC 12BIT 40CH 5V 100-LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數:8 數據接口:串行 轉換器數目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5382BST-3 | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:32/40-CHANNEL 3V/5V SINGLE SUPPLY 12/14-BIT VOUT DAC - Bulk |
| AD5382BST-3-REEL | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP T/R |
| AD5382BST-5 | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:32-CHN 5V SINGLE SUPPLY 14-BIT VOUT I.C. - Bulk |
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