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| 型號： | AD5381BSTZ-3-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 40CH 3V 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5381,3 Redesign Change 24/Oct/2011 |
| 設(shè)計資源： | 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5381 (CN0010) AD5381 Channel Monitor Function (CN0013) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 80mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 40 電壓，單極 |
| 采樣率（每秒）： | 167k |
| 其它名稱： | AD5381BSTZ-3-REELDKR |
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AD5381
Data Sheet
Rev. D | Page 28 of 40
I2C SERIAL INTERFACE
The AD5381 features an I2C-compatible2-wire interface
consisting of a serial data line (SDA)and a serial clock line
(SCL). SDA and SCL facilitate communication between the
AD5381 and the master at ratesup to 400 kHz. Figure 6 shows
the 2-wire interface timing diagrams that incorporatethree
different modes of operation. In selecting the I2C operating
mode, first configure serial operating mode (SER/PAR = 1)
and then select I2C mode by configuring the SPI/I2C pin to a
Logic 1. The device is connected to the I2C bus as a slave device
(that is, no clock is generated by the AD5381). The AD5381 has
a 7-bit slave address 1010 1(AD1)(AD0). The 5 MSB are hard-
coded and the 2 LSB are determinedby the stateof the AD1
and AD0 pins. The facility to hardware configure AD1 and AD0
allows four of these devices to be configured on the bus.
I2C Data Transfer
One data bit is transferred during each SCL clockcycle. The
data on SDA must remain stable during the high period of the
SCL clock pulse. Changesin SDA while SCL is high are control
signals that configure START and STOP conditions. Both SDA
and SCL are pulled high by the external pull-up resistors when
the I2C bus is not busy.
START and STOP Conditions
A master device initiates communication by issuing a START
condition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high. A START condition
from the mastersignals the beginning of a transmission to
the AD5381. The STOP condition frees the bus. If a repeated
START condition (Sr) is generatedinsteadof a STOP condition,
the bus remains active.
Repeated START Conditions
A repeated START (Sr)condition may indicate a change of data
direction on the bus. Sr can be used when the bus masteris
writing to several I2C devices and wants to maintain control of
the bus.
Acknowledge Bit (ACK)
The acknowledge bit (ACK)is the ninth bit attached to any
8-bit data-word. ACKis always generatedby the receiving
device. The AD5381 devices generatean ACK whenreceiving
an address or data by pulling SDA low during the ninth clock
period. Monitoring ACK allowsfor detection of unsuccess-
ful data transfers. An unsuccessful data transfer occurs if a
receiving device is busy or if a system fault has occurred.
In the event of an unsuccessful data transfer, the busmaster
should reattempt communication.
AD5381 Slave Addresses
A bus masterinitiates communication with a slave device by
issuing a START condition followed by the 7-bit slave address.
When idle, the AD5381 waits for a START condition followed
by its slave address. TheLSB of the addresswordis the Read/
Write (R/W) bit. The AD5381is a receive only device; when
communicating with the AD5381, R/W = 0. After receiving the
proper address 1010 1(AD1)(AD0), the AD5381 issues an ACK
by pulling SDA low for one clockcycle.
The AD5381 has four different user programmable addresses
determined by the AD1 and AD0 bits.
Write Operation
There are threespecificmodes in which data can be written to
the AD5381 DAC.
4-Byte Mode
When writing to the AD5381 DACs, the user must begin
with an address byte(R/W = 0)after which the DAC acknowl-
edges that it is prepared to receive databy pulling SDA low.
The address byteis followed by the pointer byte; this addresses
the specific channel in the DAC to be addressed andis also
acknowledged by the DAC. Twobytesof data are then written
to the DAC, as shown in Figure 31. A STOP condition follows.
This allows the user to update a single channel within the
AD5381 at any time and requires fourbytes of datato be
transferred fromthe master.
3-Byte Mode
In 3-byte mode,the user can update morethan one channel in a
write sequence without having to write the device addressbyte
each time. The device address byte is only required once;sub-
sequent channel updates requirethe pointer byteand the data
bytes. In 3-byte mode, the userbegins with an address byte
(R/W = 0), after which the DAC willacknowledge that it is pre-
pared to receive databy pulling SDA low. The addressbyteis
followed by the pointer byte. This addresses thespecificchannel
in the DAC to be addressed and is also acknowledged by the
DAC. This is then followed by the two databytes. REG1 and
REG0 determine the register to be updated.
If a STOP condition doesnot follow thedatabytes, another
channel can be updated by sending a newpointerbyte followed
by the data bytes. Thismode only requires threebytes tobe
sent to updateany channel oncethe device hasbeen initially
addressed, andreduces thesoftwareoverhead in updating the
AD5381 channels.A STOP condition atany timeexitsthis mode.
Figure 32 showsa typical configuration.
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| AD5381BSTZ-5 | 功能描述:IC DAC 12BIT 40CH 5V 100-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5381BSTZ-5-REEL | 功能描述:IC DAC 12BIT 40CH 5V 100-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5382BST-3 | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:32/40-CHANNEL 3V/5V SINGLE SUPPLY 12/14-BIT VOUT DAC - Bulk |
| AD5382BST-3-REEL | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP T/R |
| AD5382BST-5 | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:32-CHN 5V SINGLE SUPPLY 14-BIT VOUT I.C. - Bulk |
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