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參數(shù)資料
| 型號： | AD5381BSTZ-3-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 40CH 3V 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5381,3 Redesign Change 24/Oct/2011 |
| 設(shè)計資源： | 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5381 (CN0010) AD5381 Channel Monitor Function (CN0013) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 80mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 40 電壓，單極 |
| 采樣率（每秒）： | 167k |
| 其它名稱： | AD5381BSTZ-3-REELDKR |
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AD5381
Data Sheet
Rev. D | Page 30 of 40
2-Byte Mode
Following initialization of 2-byte mode, the usercan update
channels sequentially. The device address byte is only required
once and the pointer address pointeris configured for auto-
increment or burst mode.
The user must begin with an addressbyte(R/W = 0), after
which the DAC acknowledges that it is preparedto receive
data by pulling SDA low. The addressbyteis followed by a
specific pointer byte (0xFF)that initiates the burst mode of
operation. The address pointer initializes to Channel 0, the data
following the pointer is loaded to Channel 0, and the address
pointer automatically incrementsto the next address.
The REG0 and REG1 bits in the data byte determinewhich
register will be updated. In this mode, following the initializa-
tion, only the two data bytes are required to updatea channel.
The channel addressautomatically increments fromAddress 0
to Channel 39 and then returns to the normal 3-bytemodeof
operation. This modeallows transmission of datato all
channels in one block and reduces the software overhead in
configuring all channels. A STOP condition at any time exits
this mode. Toggle mode is not supported in 2-byte mode.
Figure 33 shows a typical configuration.
PARALLEL INTERFACE
The SER/PAR pin must be tied low to enable the parallel
interface and disable the serial interfaces.Figure 7 shows the
timing diagram for a parallel write. The parallel interface is
controlled by the following pins.
CS Pin
Active low device select pin.
WR Pin
On the rising edge of WR, with CSlow, the addresseson Pin A5
to Pin A0 are latched; data present on the data bus is loaded into
the selected input registers.
REG0, REG1 Pins
The REG0 and REG1 pins determine the destination registerof
the data being written to the AD5381. See Table 10.
Pin A5 to Pin A0
Each of the 40 DAC channels can be individually addressed.
Pin DB11 to Pin DB0
The AD5381 accepts a straight 12-bit parallel word on DB11 to
DB0, where DB11 is the MSB and DB0 is the LSB.
1
0
1
0
1
AD1
AD0
R/W
A7 = 1
A6 = 1
A5 = 1
A4 = 1
A3 = 1
A2 = 1
A1 = 1
A0 = 1
START COND
BY MASTER
ADDRESS BYTE
POINTER BYTE
MOST SIGNIFICANT DATA BYTE
CHANNEL 0 DATA
LEAST SIGNIFICANT DATA BYTE
ACK BY
CONVERTER
MSB
ACK BY
CONVERTER
ACK BY
AD538x
ACK BY
AD538x
MOST SIGNIFICANT DATA BYTE
CHANNEL 1 DATA
LEAST SIGNIFICANT DATA BYTE
ACK BY
CONVERTER
ACK BY
CONVERTER
MOST SIGNIFICANT DATA BYTE
CHANNEL N DATA FOLLOWED BY STOP
LEAST SIGNIFICANT DATA BYTE
ACK BY
CONVERTER
ACK BY
CONVERTER
STOP
COND
BY
MASTER
REG1
REG0
MSB
LSB
MSB
LSB
REG1
REG0
MSB
LSB
MSB
LSB
REG1
REG0
MSB
LSB
MSB
LSB
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
03732-
033
Figure 33. 2-Byte, 12C Write Operation
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| AD5381BSTZ-5 | 功能描述:IC DAC 12BIT 40CH 5V 100-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5381BSTZ-5-REEL | 功能描述:IC DAC 12BIT 40CH 5V 100-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5382BST-3 | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:32/40-CHANNEL 3V/5V SINGLE SUPPLY 12/14-BIT VOUT DAC - Bulk |
| AD5382BST-3-REEL | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP T/R |
| AD5382BST-5 | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:32-CHN 5V SINGLE SUPPLY 14-BIT VOUT I.C. - Bulk |
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