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| 型號(hào)： | AD5370BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 9/29頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT 40CH SERIAL 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 設(shè)計(jì)資源： | 40 Channels of Programmable Output Span Using AD5371 (CN0149) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 設(shè)置時(shí)間： | 20µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 610mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類(lèi)型： | 40 電壓，單極；40 電壓，雙極 |
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AD5370
Rev. 0 | Page 16 of 28
A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT
Each DAC channel has seven data registers. The actual DAC
data-word can be written to either the X1A or X1B input register,
depending on the setting of the A/B bit in the Control register.
If the A/B bit is 0, data is written to the X1A register. If the A/B
bit is 1, data is written to the X1B register. Note that this single
bit is a global control and affects every DAC channel in the
device. It is not possible to set up the device on a per-channel
basis so that some writes are to X1A registers and some writes
are to X1B registers.
MUX
DAC
REGISTER
MUX
X1A
REGISTER
X1B
REGISTER
M
REGISTER
C
REGISTER
X2A
REGISTER
X2B
REGISTER
05
81
3-
02
0
Figure 19. Data Registers Associated with Each DAC Channel
Each DAC channel also has a gain (M) register and an offset (C)
register, which allow trimming out of the gain and offset errors
of the entire signal chain. Data from the X1A register is operated on
by a digital multiplier and an adder controlled by the contents of
the M and C registers. The calibrated DAC data is then stored in
the X2A register. Similarly, data from the X1B register is operated
on by the multiplier and adder and stored in the X2B register.
Although Figure 19 indicates a multiplier and an adder for each
channel, there is only one multiplier and one adder in the device,
and they are shared among all channels. This has implications
for the update speed when several channels are updated at once,
as described in the Register Update Rates section.
Each time data is written to the X1A register, or to the M or C
register with the A/B control bit set to 0, the X2A data is recal-
culated and the X2A register is automatically updated. Similarly,
X2B is updated each time data is written to X1B or to M or C
with A/B set to 1. The X2A and X2B registers are not readable
or directly writable by the user.
Data output from the X2A and X2B registers is routed to the
final DAC register by a multiplexer. Whether each individual
DAC takes its data from the X2A or X2B register is controlled
by an 8-bit A/B select register associated with each group of
eight DACs. If a bit in this register is 0, the DAC takes its data
from the X2A register; if 1, the DAC takes its data from the X2B
register (Bit 0 through Bit 7 control DAC0 to DAC7).
Note that, because there are 40 bits in five registers, it is possible
to set up, on a per-channel basis, whether each DAC takes its
data from the X2A or X2B register. A global command is also
provided, which sets all bits in the A/B select registers to 0 or to 1.
LOAD DAC
All DAC channels in the AD5370 can be updated simultane-
ously by taking LDAC low when each DAC register is updated
from either its X2A or X2B register, depending on the setting of
the A/B select registers. The DAC register is not readable or
directly writable by the user.
OFFSET DAC CHANNELS
In addition to the gain and offset trim for each DAC channel,
there are two 14-bit offset DAC channels, one for Group 0 and
one for Group 1 to Group 4. These allow the output range of all
DAC channels connected to them to be offset within a defined
range. Thus, subject to the limitations of headroom, it is possible to
set the output range of Group 0 or Group 1 to Group 4 to be
unipolar positive, unipolar negative, or bipolar, either symmetrical
or asymmetrical about 0 V. The DAC channels in the AD5370
are factory trimmed with the offset DAC channels set at their
default values. This results in optimum offset and gain performance
for the default output range and span.
When the output range is adjusted by changing the value of the
offset DAC channel, an extra offset is introduced due to the
gain error of the offset DAC channel. The amount of offset is
dependent on the magnitude of the reference and how much
the offset DAC channel deviates from its default value. This
offset is quoted in the Specifications section.
The worst-case offset occurs when the offset DAC channel is at
positive or negative full scale. This value can be added to the
offset present in the main DAC channel to give an indication of
the overall offset for that channel. In most cases, the offset can be
removed by programming the channel’s C register with an
appropriate value. The extra offset caused by the offset DAC s
only needs to be taken into account when an offset DAC
channel is changed from its default value.
Figure 20 shows the allowable code range that can be loaded to
the offset DAC channel; this is dependent on the reference value
used. Thus, for a 5 V reference, the offset DAC channel should
not be programmed with a value greater than 8192 (0x2000).
0
4096
8192
12288
16383
OFFSET DAC CODE
0
1
2
3
4
V
R
E
F
(V
)
5
RESERVED
05
81
3-
0
21
Figure 20. Offset DAC Code Range
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| AD5371BBCZ-REEL | 功能描述:IC DAC 14BIT 40CH SER 100-CSPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類(lèi)型:8 電壓，單極 采樣率（每秒）:* |
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