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參數(shù)資料
| 型號： | AD5370BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/29頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT 40CH SERIAL 64-LQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 設計資源： | 40 Channels of Programmable Output Span Using AD5371 (CN0149) |
| 標準包裝： | 1,500 |
| 設置時間： | 20µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 40 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 610mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 40 電壓，單極；40 電壓，雙極 |
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AD5370
Rev. 0 | Page 17 of 28
OUTPUT AMPLIFIER
The output amplifiers can swing to 1.4 V below the positive
supply and 1.4 V above the negative supply, which limits how
much the output can be offset for a given reference voltage. For
example, it is not possible to have a unipolar output range of 20 V
because the maximum supply voltage is ±16.5 V.
CLR
DAC
CHANNEL
OFFSET
DAC
VOUT
R6
10k
R2
20k
S3
S2
S1
R4
60k
R3
20k
SIGGND
R5
60k
R1
20k
05
81
3-
0
22
Figure 21. Output Amplifier and Offset DAC
Figure 21 shows details of a DAC output amplifier and its
connections to its corresponding offset DAC. On power-up, S1
is open, disconnecting the amplifier from the output. S3 is
closed; thus, the output is pulled to the corresponding SIGGND
(R1 and R2 are much greater than R6). S2 is also closed to
prevent the output amplifier being open-loop. If CLR is low at
taken high. The DAC registers can be programmed, and the
outputs assume the programmed values when CLR is taken
high. Even if CLR is high at power-up, the output remains in the
previously described condition until VDD > 6 V and VSS
< 4 V and the initialization sequence has finished. The outputs
then go to their power-on default values.
TRANSFER FUNCTION
DAC CODE
FULL-SCALE
ERROR
+
ZERO-SCALE
ERROR
ZERO-SCALE
ERROR
–4V
0
16383
8V
IDEAL
TRANSFER
FUNCTION
ACTUAL
TRANSFER
FUNCTION
OUTPUT
VOLTAGE
05
81
3-
0
08
Figure 22. DAC Transfer Function
The output voltage of a DAC in the AD5370 is dependent on the
value in the input register, the value of the M and C registers,
and the value in the offset DAC. The transfer functions for the
AD5370 are shown in the following section.
The input code is the value in the X1A or X1B register that is
applied to DAC (X1A, X1B default code = 5461), as follows:
15
16
2
)
1
(
_
+
×
=
C
M
CODE
INPUT
CODE
DAC
DAC output voltage is calculated as follows:
(
)
SIGGND
V
CODE
OFFSET
CODE
DAC
VREF
VOUT
+
×
×
=
16
2
_
4
_
4
where:
DAC_CODE should be within the range of 0 to 65,535.
For 12 V span, VREF = 3.0 V.
For 20 V span, VREF = 5.0 V.
M = code in gain register default code = 216 – 1.
C = code in offset register default code = 215.
OFFSET_CODE is the code loaded to the offset DAC. It is
multiplied by 4 in the transfer function because the offset DAC
is a 14-bit device. On power-up, the default code loaded to the
offset DAC is 5461 (0x1555). With a 3 V reference, this gives a
span of 4 V to +8 V.
REFERENCE SELECTION
The AD5370 has two reference input pins. The voltage applied
to the reference pins determines the output voltage span on
VOUT0 to VOUT39. VREF0 determines the voltage span for
VOUT0 to VOUT7 (Group 0) and VREF1 determines the
voltage span for VOUT8 to VOUT39 (Group 2 to Group 4).
The reference voltage applied to each VREF pin can be
different, if required, allowing each group to have a different
voltage span. The output voltage range and span can be adjusted
further by programming the offset and gain registers for each
channel and by programming the offset DAC channels. If the
offset and gain features are not used (that is, the M and C
registers are left at their default values), the required reference
levels can be calculated as follows:
VREF = (VOUTMAX VOUTMIN)/4
If the offset and gain features of the AD5370 are used, the
required output range is slightly different. The chosen output
range should take into account the system offset and gain errors
that need to be trimmed out. Therefore, the chosen output
range should be larger than the actual required range.
The required reference levels can be calculated as follows:
1.
Identify the nominal output range on VOUT.
2.
Identify the maximum offset span and the maximum gain
required on the full output signal range.
3.
Calculate the new maximum output range on VOUT,
including the expected maximum offset and gain errors.
4.
Choose the new required VOUTMAX and VOUTMIN, keeping
the VOUT limits centered on the nominal values. Note that
VDD and VSS must provide sufficient headroom.
5.
Calculate the value of VREF as follows:
VREF = (VOUTMAX VOUTMIN)/4
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD5370BSTZ-U2 | 制造商:Analog Devices 功能描述:40-CH 16-BIT SERIAL BIPOLAR DAC I.C. - Bulk |
| AD5371 | 制造商:AD 制造商全稱:Analog Devices 功能描述:40-Channel, 14-Bit Serial Input, Voltage-Output DAC |
| AD5371BBCZ | 功能描述:IC DAC 14BIT 40CH SER 100-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5371BBCZ-REEL | 功能描述:IC DAC 14BIT 40CH SER 100-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5371BSTZ | 功能描述:IC DAC 14BIT 40CH SER 80-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
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