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參數(shù)資料
| 型號(hào)： | AD5370BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 8/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 40CH SERIAL 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 設(shè)計(jì)資源： | 40 Channels of Programmable Output Span Using AD5371 (CN0149) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 設(shè)置時(shí)間： | 20µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 610mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 40 電壓，單極；40 電壓，雙極 |
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AD5370
Rev. 0 | Page 15 of 28
THEORY OF OPERATION
DAC ARCHITECTURE
The AD5370 contains 40 DAC channels and 40 output amplifiers
in a single package. The architecture of a single DAC channel
consists of a 16-bit resistor-string DAC followed by an output
buffer amplifier. The resistor-string section is simply a string of
resistors, of equal value, from VREF to AGND. This type of
architecture guarantees DAC monotonicity. The 16-bit binary
digital code loaded to the DAC register determines at which
node on the string the voltage is tapped off before being fed into
the output amplifier. The output amplifier multiplies the DAC
output voltage by 4. The nominal output span is 12 V with a 3 V
reference and 20 V with a 5 V reference.
CHANNEL GROUPS
The 40 DAC channels of the AD5370 are arranged into five
groups of eight channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. Group 1 to Group 4 derive
their reference voltage from VREF1. Each group has its own
signal ground pin.
Table 7. AD5370 Registers
Register
Name
Word
Length
(Bits)
Default
Value
Description
X1A
16
0x1555
Input Data Register A. One for each DAC channel.
X1B
16
0x1555
Input Data Register B. One for each DAC channel.
M
16
0x3FFF
Gain trim register. One for each DAC channel.
C
16
0x2000
Offset trim register. One for each DAC channel.
X2A
16
Not user
accessible
Output Data Register A. One for each DAC channel. These registers store the final calibrated DAC
data after gain and offset trimming. They are not readable or directly writable.
X2B
16
Not user
accessible
Output Data Register B. One for each DAC channel. These registers store the final calibrated DAC
data after gain and offset trimming. They are not readable or directly writable.
DAC
Not user
accessible
Data registers from which the DAC channels take their final input data. The DAC registers are
updated from the X2A or X2B register. They are not readable or directly writable.
OFS0
14
0x1555
Offset DAC 0 data register. Sets the offset for Group 0.
OFS1
14
0x1555
Offset DAC 1 data register. Sets the offset for Group 1 to Group 4.
Control
3
0x00
Bit 2 = A/B.
0 = global selection of X1A input data registers.
1 = X1B registers.
Bit 1 = enable temperature shutdown.
0 = disable temperature shutdown.
1 = enable.
Bit 0 = soft power-down.
0 = soft power-up.
1 = soft power-down.
A/B Select 0
8
0x00
Each bit in this register determines if a DAC channel in Group 0 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
A/B Select 1
8
0x00
Each bit in this register determines if a DAC channel in Group 1 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
A/B Select 2
8
0x00
Each bit in this register determines if a DAC channel in Group 2 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
A/B Select 3
8
0x00
Each bit in this register determines if a DAC channel in Group 3 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
A/B Select 4
8
0x00
Each bit in this register determines if a DAC channel in Group 4 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
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| AD5371 | 制造商:AD 制造商全稱:Analog Devices 功能描述:40-Channel, 14-Bit Serial Input, Voltage-Output DAC |
| AD5371BBCZ | 功能描述:IC DAC 14BIT 40CH SER 100-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5371BBCZ-REEL | 功能描述:IC DAC 14BIT 40CH SER 100-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
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