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| 型號： | AD5370BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/29頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT 40CH SERIAL 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 設(shè)計資源： | 40 Channels of Programmable Output Span Using AD5371 (CN0149) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 設(shè)置時間： | 20µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 610mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 40 電壓，單極；40 電壓，雙極 |
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AD5370
Rev. 0 | Page 21 of 28
SERIAL INTERFACE
The AD5370 contains a high speed SPI-compatible serial interface
operating at clock frequencies up to 50 MHz (20 MHz for read
operations). To minimize both the power consumption of the
device and on-chip digital noise, the interface powers up fully
only when the device is being written to, that is, on the falling
edge of SYNC. The serial interface is 2.5 V LVTTL-compatible
when operating from a 2.5 V to 3.6 V DVCC supply. It is con-
trolled by four pins: SYNC (frame synchronization input), SDI
(serial data input pin), SCLK (clocks data in and out of the device),
and SDO (serial data output pin for data readback).
SPI WRITE MODE
The AD5370 allows writing of data via the serial interface to
every register directly accessible to the serial interface, which is
all registers except the X2A and X2B registers and the DAC
registers. The X2A and X2B registers are updated when the user
writes to the X1A, X1B, M, or C register, and the DAC registers
are updated by LDAC.
The serial word (see Table 10) is 24 bits long; 16 of these bits are
data bits, six bits are address bits, and two bits are mode bits that
determine what is done with the data.
The serial interface works with both a continuous and a burst
(gated) serial clock. Serial data applied to SDI is clocked into
the AD5370 by clock pulses applied to SCLK. The first falling
edge of SYNC starts the write cycle. At least 24 falling clock edges
must be applied to SCLK to clock in 24 bits of data before SYNC
is taken high again. If SYNC is taken high before the 24th falling
clock edge, the write operation is aborted.
If a continuous clock is used, SYNC must be taken high before
the 25th falling clock edge. This inhibits the clock within the
AD5370. If more than 24 falling clock edges are applied before
SYNC is taken high again, the input data becomes corrupted. If
an externally gated clock of exactly 24 pulses is used, SYNC can
be taken high any time after the 24th falling clock edge.
The input register addressed is updated on the rising edge of
SYNC. For another serial transfer to take place, SYNC must be
taken low again.
SPI READBACK MODE
The AD5370 allows data readback via the serial interface from
every register directly accessible to the serial interface, which is
all registers except the X2A, X2B, and DAC registers. To read
back a register, it is first necessary to tell the AD5370 which
register to read. This is achieved by writing a word whose
first two bits are the Special Function Code 00 to the device. The
remaining bits then determine which register is to be read back.
If a readback command is written to a special function register,
data from the selected register is clocked out of the SDO pin
during the next SPI operation. The SDO pin is normally three-
stated but becomes driven as soon as a read command is issued.
The pin remains driven until the register data is clocked out.
See Figure 5 for the read timing diagram. Note that, due to the
timing requirements of t5 (25 ns), the maximum speed of the
SPI interface during a read operation should not exceed 20 MHz.
REGISTER UPDATE RATES
The value of the X2A or X2B register is calculated each time the
user writes new data to the corresponding X1, C, or M register.
The calculation is performed by a three-stage process. The first
two stages take approximately 600 ns each, and the third stage
takes approximately 300 ns. When the write to the X1, C, or M
register is complete, the calculation process begins. If the write
operation involves the update of a single DAC channel, the user
is free to write to another register, provided that the write
operation does not finish until the first stage calculation is
complete, that is, 600 ns after completion of the first write
operation. If a group of channels is being updated by a single
write operation, the first stage calculation is repeated for each
channel, taking 600 ns per channel. In this case, the user should not
complete the next write operation until this time has elapsed.
CHANNEL ADDRESSING AND SPECIAL MODES
If the mode bits are not 00, the data-word for D13 to D0 is
written to the device. Address Bit A5 to Address Bit A0
determine which channels are written to, whereas the mode bits
determine the register (X1A, X1B, C, or M) to which the data is
written, as shown in Table 9. If data is to be written to the X1A or
X1B register, the setting of the A/B bit in the control register
determines the register to which the data is written (that is,
0 → X1A, 1 → X1B).
Table 9. Mode Bits
M1
M0
Action
1
Writes to the DAC input data (X) register,
depending on the control register A/B bit
1
0
Writes to the DAC offset (C) register
0
1
Writes to the DAC gain (M) register
0
Special function, used in combination
with other bits of the data-word
Table 10. Serial Word Bit Assignment
I23
I22
I21
I20
I19
I18
I17
I16
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
M1
M0
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
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