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| 型號： | AD5370BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 40CH SERIAL 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 設(shè)計資源： | 40 Channels of Programmable Output Span Using AD5371 (CN0149) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 設(shè)置時間： | 20µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 610mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 40 電壓，單極；40 電壓，雙極 |
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AD5370
Rev. 0 | Page 19 of 28
RESET FUNCTION
The reset function is initiated by the RESET pin. On the rising
edge of RESET, the AD5370 state machine initiates a reset
sequence to reset the X, M, and C registers to their default
values. This sequence typically takes 300 μs, and the user should
not write to the part during this time. On power-up, it is recom-
mended that the user bring RESET high as soon as possible to
properly initialize the registers.
When the reset sequence is complete (and provided that CLR is
high), the DAC output is at a potential specified by the default
register settings, which are equivalent to SIGGNDx. The DAC
outputs remain at SIGGNDx until the X, M, or C register is
updated and LDAC is taken low. The AD5370 can be returned
to the default state by pulsing RESET low for at least 30 ns. Note
that, because the reset function is triggered on the rising edge,
bringing RESET low has no effect on the operation of the AD5370.
CLEAR FUNCTION
CLR is an active low input that should be high for normal
operation. The CLR pin has in internal 500 kΩ pull-down
resistor. When CLR is low, the input to each of the DAC output
buffer stages, VOUT0 to VOUT39, is switched to the externally
set potential on the relevant SIGGND pin. While CLR is low, all
LDAC pulses are ignored. When CLR is taken high again, the
DAC outputs remain cleared until LDAC is taken low. The contents
of the input registers and DAC registers are not affected by taking
CLR low. To prevent glitches from appearing on the outputs, CLR
should be brought low by writing to the offset DAC whenever
the output span is adjusted.
BUSY AND LDAC FUNCTIONS
The value of an X2 (A or B) register is calculated each time the
user writes new data to the corresponding X1, C, or M register.
During the calculation of X2, the BUSY output goes low. While
BUSY is low, the user can continue writing new data to the X1,
M, or C register (see the Register Update Rates section for more
details), but no DAC output updates can take place.
The BUSY pin is bidirectional and has a 50 kΩ internal pull-up
resistor. In cases where multiple AD5370 devices are used in
one system, the BUSY pins can be tied together. This is useful
when it is required that no DAC channel in any device be
updated until all other DAC channels are ready to be updated.
When each device finishes updating the X2 (A or B) register, it
releases the BUSY pin. If another device has not finished
updating its X2 register, it holds BUSY low, thus delaying the
effect of LDAC going low.
The DAC outputs are updated by taking the LDAC input low. If
LDAC goes low while BUSY is active, the LDAC event is stored
and the DAC outputs update immediately after BUSY goes
high. A user can also hold the LDAC input permanently low. In
this case, the DAC outputs update immediately after BUSY goes
high. Whenever the A/B select registers are written to, BUSY
also goes low, for approximately 600 ns.
The AD5370 has flexible addressing that allows writing of data
to a single channel, all channels in a group, the same channel in
Group 0 to Group 4 or the same channel in Group 1 to Group 4,
or all channels in the device. This means that 1, 4, 5, 8, or 40
DAC register values may need to be calculated and updated.
Because there is only one multiplier shared among 40 channels,
this task must be done sequentially so that the length of the
BUSY pulse varies according to the number of channels being
updated.
Table 8. BUSY Pulse Widths
Action
BUSY Pulse Width1
(μs max)
Loading X1A, X1B, C, or M to 1 channel2
1.5
Loading X1A, X1B, C, or M to 4 channels
3.3
Loading X1A, X1B, C, or M to 5 channels
3.9
Loading X1A, X1B, C, or M to 8 channels
5.7
Loading X1A, X1B, C, or M to 40 channels
24.9
1
BUSY Pulse Width = ((Number of Channels + 1) × 600 ns) + 300 ns.
2 A single channel update is typically 1 μs.
The AD5370 contains an extra feature whereby a DAC register
is not updated unless its X2A or X2B register has been written
to since the last time LDAC was brought low. Normally, when
LDAC is brought low, the DAC registers are filled with the
contents of the X2A or X2B register, depending on the setting of
the A/B select registers. However, the AD5370 updates the DAC
register only if the X2 data has changed, thereby removing
unnecessary digital crosstalk.
POWER-DOWN MODE
The AD5370 can be powered down by setting Bit 0 in the
control register to 1. This turns off the DAC channels, thus
reducing the current consumption. The DAC outputs are
connected to their respective SIGGND potentials. The power-
down mode does not change the contents of the registers, and
the DAC channels return to their previous voltage when the
power-down bit is cleared to 0.
THERMAL SHUTDOWN FUNCTION
The AD5370 can be programmed to power down the DACs if
the temperature on the die exceeds 130°C. Setting Bit 1 in the
control register to 1 (see the Special Function Mode section)
enables this function. If the die temperature exceeds 130°C, the
AD5370 enters a temperature power-down mode, which is
equivalent to setting the power-down bit in the control register.
To indicate that the AD5370 has entered temperature shutdown
mode, Bit 4 of the control register is set to 1. The AD5370 remains
in temperature shutdown mode, even if the die temperature
falls, until Bit 1 in the control register is cleared to 0.
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