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參數(shù)資料
| 型號： | AD53020 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Four Channel ECL Delay Line(四通道ECL延遲線) |
| 中文描述： | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 4/4頁 |
| 文件大?。?/td> | 88K |
| 代理商： | AD53020 |
AD53020
–4–
REV. 0
C
P
A second bias current reference is employed to set the bias
current of the delay cells. T his current is set by the external
resistor at REX T 2. A 2.94 k
resistor sets the nominal bias
current of 500
μ
A. T he nominal voltage at the REX T 2 pin
is –1.47 V.
T he current references require compensation capacitors of
0.1
μ
F to V
EE
at each of the COMP1 and COMP2 pins. In
addition, each V
EE
supply pin should also have its own decou-
pling capacitor of 0.1
μ
F to ground.
All decoupling capacitors should be located as close as possible
to the AD53020 chip.
T he mode is set by the inputs S0 and S1. T hese pins use stan-
dard ECL levels, with the addition of a third level for the S1
Pin, which can also be connected to V
EE
. Refer to T able I for
the description of the modes and their respective settings.
For Modes 2 and 3, it is important to note that an internal flip-
flop is used to provide the independent control of rising and
falling edges. T he state of this flip-flop is indeterminate upon
power-up. T he state becomes fixed once the first full pulse is
provided to each channel, consisting of a positive edge followed
by a negative edge.
T able I. T ruth T able for Mode Determination
T ypical Independent Adjustment of
Span
Positive and Negative E dges
S1
S0
Mode
0
0
1
1
V
EE
V
EE
0
1
0
1
0
1
0
1
2
3
Not Valid
5
19 ns
31 ns
19 ns
31 ns
No
No
Yes
Yes
45 ns
No
S0 and S1 accept logical ECL levels. In the case of S1 only, a third state is also
accepted, at the negative supply, V
EE
.
6
IDPIN 1
7
40
39
17
18
29
28
(PINS DOWN)
0.695 (17.65)
0.656 (16.66)
0.048 (1.21)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
0.021 (0.53)
0.013 (0.33)
0.050
(1.27)
BSC
0.63 (16.00)
0.59 (14.99)
0.032 (0.81)
0.026 (0.66)
0.180 (4.57)
0.165 (4.19)
0.040 (1.01)
0.025 (0.64)
0.025 (0.63)
0.015 (0.38)
0.110 (2.79)
0.085 (2.16)
0.056 (1.42)
0.042 (1.07)
44-Lead PLCC
(P-44A)
OUT LINE DIME NSIONS
Dimensions shown in inches and (mm).
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