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參數(shù)資料
| 型號： | AD5317 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Rail-To-Rail,Voltage Output 10-Bit DACs(滿幅度電壓輸出雙10位D/A轉(zhuǎn)換器) |
| 中文描述： | 雙通道軌至軌電壓輸出10位DAC（滿幅度電壓輸出雙10位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 336K |
| 代理商： | AD5317 |
The references for the four DACs are derived from two reference
pins (one per DAC pair). These reference inputs can be config-
ured as buffered or unbuffered inputs depending on the state of
the BUF bit in the input word. The parts incorporate a power-
on-reset circuit that ensures that the DAC outputs power up to
zero volts and remain there until a valid write takes place to the
device. There is also an asynchronous active-low
CLR
pin which
clears all DACs to 0V. The outputs of all DACs may be updated
simultaneously using the asynchronous
LDAC
input. The parts
contain a power-down feature which reduces the current con-
sumption of the devices to 200nA at 5V (50nA at 3V). The out-
puts are in a high-impedance state while in power-down mode.
All DACs are powered-down together using the active-low
PD
pin.
SPI
,
QSPI
are Trademarks of Motorola.
MICROWIRE
is a Trademark of National Semiconductor.
a
Prelim Technical Information
AD5307/17
FEATURES
AD5307: Four 8-Bit DACs in One Package
AD5317: Four 10-Bit DACs in One Package
16-Pin TSSOP Package
Micro-Power Operation: 500
μ
A @ 5V (Including
Reference Current)
Power Down to 200nA@5V, 50nA@3V
+2.5V to +5.5V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic By Design
Buffered/Unbuffered Reference Input Options
Output Range: 0-Vref or 0-2Vref
Power-On-Reset to Zero Volts
SDO Daisy-Chaining Option
Simultaneous Update of DAC Outputs
Asynchronous Clear Facility
Low-Power Serial Interface with Schmitt-Triggered
Inputs
On-Chip Output Buffer Amplifiers with Rail-to-Rail
Operation
SYNC
Interrupt Facility
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD5307/17 are quad 8 and 10-bit buffered voltage-output
DACs which operate from a single +2.5V to +5.5V supply. Their
on-chip precision output amplifiers allow rail-to-rail output
swing to be achieved. The AD5307/17 utilize a versatile 3-wire
serial interface which operates at clock rates up to 30MHz and is
compatible with standard SPI, QSPI, MICROWIRE and
DSP interface standards.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 781/329-4700
WWW site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
The output ranges for any or all DACs can be set at 0-V
REF
or 0-
2V
REF
depending on the Gain bit. The parts may also be used in
daisy-chaining applications using the SDO pin.
The four control bits in the 16-bit serial input word are used to
address the relevant DAC, to select the output range and to se-
lect the reference mode (buffered or unbuffered).
The low power consumption of these parts in normal operation
make them ideally suited to portable battery-operated equip-
ment. The power consumption is 2.5mW at 5V reducing to 1μW
in power-down mode.
The AD5307 and AD5317 are both available in a 16-pin TSSOP
package.
PRODUCT HIGHLIGHTS
1. Low Power, Single supply operation. These parts operate
from a single +2.5V to +5.5V supply and consume 1.2 mW at
3V and 2.5 mW at 5V making them ideal for battery-powered
applications. Since the references may be buffered internally
no external reference current is required and system power
consumption is reduced.
2. The on-chip output buffer amplifiers allow the outputs of the
DACs to swing rail-to-rail with a slew rate of 1V/μs.
3. Reference pins may be configured as buffered or
unbuffered.The unbuffered option allows the reference input
to be as high as V
DD
.
4. High speed serial interface with clock speeds up to 30MHz.
Designed for very low power consumption. The interface only
powers up during a write cycle.
5. Power-down capability. When powered down the DACs con-
sume 50nA at 3V and 200nA at 5V.
6. Output range of 0-V
REF
or 0-2V
REF
.
7. Packaged in a 16-pin TSSOP package.
Prelim.A1 4/98
+2.5 V to +5.5 V, 500uA,Quad Rail-To-Rail,
Voltage Output 8/10-Bit DACs
FUNCTIONAL BLOCK DIAGRAM
REF AB
DAC
LATCH
DAC A
INPUT
LATCH
CONTROL
LOGIC
AD5307/17
VOUT A
VOUT B
DAC
LATCH
DAC B
INPUT
LATCH
DAC
LATCH
DAC C
INPUT
LATCH
DAC
LATCH
DAC D
INPUT
LATCH
VOUT C
VOUT D
REF CD
CLR
GND
VDD
LDAC
SYNC
CLK
SDIN
POWER-ON
RESET
PD
DCEN
SDO
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