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參數(shù)資料
| 型號(hào)： | AD5317 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Rail-To-Rail,Voltage Output 10-Bit DACs(滿幅度電壓輸出雙10位D/A轉(zhuǎn)換器) |
| 中文描述： | 雙通道軌至軌電壓輸出10位DAC（滿幅度電壓輸出雙10位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 336K |
| 代理商： | AD5317 |
6
AD5307/17 Prelim Technical Information
Prelim.A1 4/98
This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a daisy-
chain. The pin should be tied low if it is being used in stand-alone mode.
Serial Data Output which can be used for daisy-chaining a number of these devices together or for reading back
the data in the shift register for diagnostic purposes. The serial data is clocked out on the falling edge of the
clock.
PIN FUNCTION DESCRIPTION
PIN NUMBERS
Pin
No.
Mnemonic
Function
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
SYNC
Analog output voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog output voltage from DAC B. The output amplifier has rail-to-rail operation.
Analog output voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog output voltage from DAC D. The output amplifier has rail-to-rail operation.
Level triggered control input (active low). This is the frame synchronization signal for the input data. When
SYNC
goes low, it enables the input shift register and data is transferred in on the falling edges of the following
clocks. The contents of the DACs are updated following the 16th clock cycle unless
SYNC
is taken high before
this edge in which case the rising edge of
SYNC
acts as an interrupt and the write sequence is ignored by the de
vice.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rate up to 30MHz.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input.
Power Supply Input. These parts can be operated from +2.5V to +5.5V and the supply should be decoupled to
GND.
Ground reference point for all circuitry on the part.
Reference Input pin for DACs A and B. This is the external reference for DACs A and B. It may be configured
as a buffered or an unbuffered input to each or both of the DACs depending on the state of the BUF bits in the
serial input words to DACs A and B. It has an input range from 0V to V
DD
in unbuffered mode and from 1V to
4V in buffered mode (V
DD
= +5V).
Reference Input pin for DACs C and D. This is the external reference for DACs C and D. It may be configured
as a buffered or an unbuffered input to each or both of the DACs depending on the state of the BUF bits in the
serial input words to DACs C and D. It has an input range from 0V to V
DD
in unbuffered mode and from 1V to
4V in buffered mode (V
DD
= +5V).
Active low control input which loads all zeroes to all input and DAC registers. Hence, the outputs also go to
0V.
Active low control input which transfers the contents of the input registers to their respective DAC registers.
Pulsing this pin low allows the simultaneous update of all DAC outputs.
Active low control input which acts as a hardware Power-Down option. This pin overrides any software power-
down option. Both DACs go into power-down mode when this pin is tied low. The DAC outputs go into a high-
impedance state and the current consumption of the part drops to 200nA @ 5V (50nA @ 3V).
SCLK
DIN
V
DD
GND
V
REF
AB
V
REF
CD
CLR
LDAC
PD
DCEN
SDO
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