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參數(shù)資料
| 型號(hào)： | AD53020 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Four Channel ECL Delay Line(四通道ECL延遲線) |
| 中文描述： | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 88K |
| 代理商： | AD53020 |
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD53020
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
Four Channel ECL Delay Line
FUNCT IONAL BLOCK DIAGRAM
FEATURES
Four Delay Lines with the Ability to Independently
Adjust All Edges
Pin Compatible and Functionally Equivalent with the
BT624
Reduced Power Dissipation
44-Lead PLCC Package with Internal Heat Spreader
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Clocked ECL Circuits
PRODUCT DE SCRIPT ION
T he AD53020 is a four-channel delay line designed for use in
automatic test equipment and digital logic systems. High speed
bipolar transistors and a 44-lead plastic PLCC package with
internal heat spreader provide high frequency performance at a
minimum of space, cost and power dissipation.
Featuring full pin compatibility and functional equivalence to
the BT 624, the AD53020 offers independent analog control of
positive and negative edges with five delay ranges. T he AD53020
offers attractive performance with optimized power dissipation
and linear delay vs. program voltage control. T his device is also
very stable over operating conditions and has very low jitter.
Digital inputs are ECL compatible. T hey can either be pro-
vided independently for each channel (IN1,
IN1
through IN4,
IN4
), or fanned out to all channels from Channel 2 (IN2,
IN2
). T he choice of these two options is made by setting the
DRVMODE input, with ECL Logic 0 providing four indepen-
dent channels, and ECL Logic 1 enabling a logical OR function
between each channel and the Channel Number 2.
For maximum timing accuracy, differential signals are recom-
mended for use with the digital inputs. However, single-ended
operation is also supported and it is facilitated through the use
of the V
BB
midpoint level generated on-chip. T o make use of
this feature, connect the V
BB
output to the inverting input of
each channel. It is also advisable, when using the V
BB
output,
to decouple this signal with a 0.1
μ
F ceramic capacitor to ground.
T he outputs of the AD53020 are ECL compatible and should
be terminated by 50
to –2.0 V at the inputs of the gates
they drive.
T he delay is programmed through the VDELAY and VWIDT H
pins for each channel. T he acceptable range is –1.3 V to –0.1 V,
representing the longest and the shortest delays provided by the
device. An 0.01
μ
F ceramic capacitor to ground is recom-
mended for each input. T he bias current for each input is fixed
by an internal current mirror. T he value of the bias current is
set by the external resistor at REX T 1. A 1.3 k
resistor to
ground at this pin establishes 1 mA bias in each input. T he
nominal voltage at the REX T 1 pin is –1.3 V.
T he VDELAY affects both the positive and negative edges in all
modes. T he VWIDT H is an additional delay adjustment that is
active in Modes 2, 3 and 5. VWIDT H has no effect in Modes 0
and 1. For Modes 2 and 3, the effect of the VWIDT H adjust-
ment is to increase or decrease the delay of the negative edge
relative to the positive edge. In Mode 5, the total delay for both
positive and negative edges is set by the combination of VDELAY
and VWIDT H.
(continued on page
4)
VWIDTH1
OUT1
OUT1
VDELAY1
VWIDTH2
VDELAY2
OUT2
OUT2
VWIDTH3
VWIDTH4
OUT3
OUT3
OUT4
OUT4
VDELAY4
VDELAY3
V
BB
COMP1
COMP2
REXT1
REXT2
V
EE
GND
S0
S1
IN1,
IN1
IN2,
IN2
IN3,
IN3
IN4,
IN4
DRVMODE
AD53020
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