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參數(shù)資料
| 型號(hào)： | AD5100YRQZ-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | System-Management IC with Programmable Quad Voltage Monitoring and Supervisory Functions |
| 中文描述： | 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16 |
| 封裝： | 0.025 INCH PITCH, ROHS COMPLIANT, MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 31/32頁 |
| 文件大?。?/td> | 495K |
| 代理商： | AD5100YRQZ-RL7 |
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Preliminary Technical Data
AD5100
Psuedo CAN Bus Wake Up Mode
Using the AD5100 as indicated in Figure 30, the microprocessor
can control its own power down sequence using the CAN Bus
wake up signal. The operator must select the last setting ‘Rising
Edge Trigger/CAN wake up mode’ in the V
2MON
Turn Off
Threshold parameter (The I2C write command is
S 01011100 A
00000100 A 00001001 A P).
Now when the rising edge of the CAN Bus wake up signal is
detected by V
2MON
, the AD5100 is powered up with shutdown
pulls high. The external regulator is turned on to supply power
to the microprocessor. A reset pulse train will be generated at
the reset output if there is no watchdog activity. The pulse
Rev. PrJ | Page 31 of 32
continues until the correct watchdog signal appears at the
AD5100 WDI pin. The shutdown pin remains high as long as
the AD5100 continues to receive the correct watchdog signal.
When the microprocessor finishes its housekeeping tasks or
powers down the software rountine, it stops sending a watchdog
signal. In response, the AD5100 generates a reset. The
shutdown pin will be pulled low 2 seconds after and the
regulator output drops to 0V, which shuts down the
microprocessor. At that point, the AD5100 goes into sleep
mode.
Up Pulse(s)
AD5100
V
1MON
V
2MON
Battery
SHDN
RESET
SD
VREG
WDI
V
i
V
o
μ
P
I/O
RS
V
DD
I/O
I/O
SCL
SDA
CAN Wake
Figure 30. CAN Wake Up Mode
RESET
WDI
SHDN
V
2MON
SCL
SDA
SDA Write
SCL
Notes
6V < V
1MON
< 30V
Select V
2MON_OFF
= Rising Edge Trigger/CAN wake up mode
Figure 31. CAN Bus operation of circuit shown in Figure 30.
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