參數(shù)資料
型號(hào)： AD5100YRQZ-RL7
廠商： ANALOG DEVICES INC
元件分類： 電源管理
英文描述： System-Management IC with Programmable Quad Voltage Monitoring and Supervisory Functions
中文描述： 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16
封裝： 0.025 INCH PITCH, ROHS COMPLIANT, MO-137AB, QSOP-16
文件頁數(shù)： 22/32頁
文件大?。?/td> 495K
代理商： AD5100YRQZ-RL7
AD5100
Preliminary Technical Data
Table 9. AD5100 Register Map
Rev. PrJ | Page 22 of 32
Regi
ster
Add
ress
Re
ad
/
W
rit
e
Permane
ntly
settable
Register Name & Bit Description
Pre-OTP
Power On
Default
(1)
0x01
R/
W
Y
V
1MON
Over-Voltage Threshold
[3:0] – 4 bits used to program V
1MON
OV Threshold
[7:4] – Reserved
0x00
(18.00 V)
0x02
R/
W
Y
V
1MON
Under-Voltage Threshold
[3:0] – 4 bits used to program V
1MON
UV Threshold
[7:4] – Reserved
0x00
(8.43 V)
0x03
R/
W
Y
V
2MON
Turn-On Threshold
[3:0] – 4 bits used to program V
2MON
TON Threshold
[7:4] – Reserved
0x00
(7.47 V)
0x04
R/
W
Y
V
2MON
Turn-Off Threshold
[3:0] – 4 bits used to program V
2MON
TOFF Threshold
[7:4] – Reserved
0x00
(6.95 V)
0x05
R/
W
Y
V
3MON
RESET Threshold
[2:0] – 3 bits used to program V
3MON
RESET Threshold
[7:3] – Reserved
0x00
(4.36 V)
0x06
R/
W
Y
V
4MON
RESET Threshold
[2:0] – 3 bits used to program V
4MON
RESET Threshold
[7:3] – Reserved
0x00
(Disabled)
0x07
R/
W
Y
V
1MON
OV/UV Triggered SHDN Hold
[2:0] – 3 bits used to program V
1MON
OV/UV Triggered SHDN Hold time
[7:3] – Reserved
0x00
(200 mS)
0x08
R/
W
Y
V
1MON
OV/UV Triggered SHDN Delay
[2:0] – 3 bits used to program V
1MON
OV/UV Triggered SHDN Delay time
[7:3] – Reserved
0x00
(1200 mS)
0x09
R/
W
Y
V
2MON
Turn-On Triggered SHDN Hold
[2:0] – 3 bits used to program V
2MON
TON Triggered SHDN Hold time
[7:3] – Reserved
0x00
(10 mS)
0x0
A
R/
W
Y
V
2MON
Turn-Off Triggered SHDN Delay
[2:0] – 3 bits used to program V
2MON
TOFF Triggered SHDN Delay time
[7:3] – Reserved
0x00
(100 mS)
0x0
R/
Y
RESET Hold
0x00
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