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參數(shù)資料
| 型號： | AD5100YRQZ-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | System-Management IC with Programmable Quad Voltage Monitoring and Supervisory Functions |
| 中文描述： | 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16 |
| 封裝： | 0.025 INCH PITCH, ROHS COMPLIANT, MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 495K |
| 代理商： | AD5100YRQZ-RL7 |
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AD5100
Preliminary Technical Data
Rev. PrJ | Page 16 of 32
programming such that a broken WDI connection or any
unusual condition that makes WDI float will trigger the reset.
Enabling or disabling floating WDI can be changed
dynamically provided that the OTP fuse of such function is
not programmed or the OTP overriden function is selected.
Manual Reset
Manual Reset MR is active low and it has an internal pull-up
resistor to V
3MON
. MR can be driven from a CMOS logic
signal. The MR and RESET timing diagrams are shown in
The default Watchdog Timeout is 1500ms. User should refer
to Table 6b if they want to program a different setting.
Figure 14. MR has the highest priority in triggering the
RESET over any other monitoring inputs.
MR
RESET
< t
MR_GLITCH
t
MR_DELAY
RS_HOLD*
Programmable
t
MR
Figure 14. Manual Reset Timing Diagrams
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