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參數(shù)資料
| 型號： | AD4360-8 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | Integrated Synthesizer and VCO |
| 中文描述： | 綜合合成器和VCO |
| 文件頁數(shù)： | 16/24頁 |
| 文件大小： | 332K |
| 代理商： | AD4360-8 |
ADF4360-8
Table 9. R Counter Latch
Rev. A | Page 16 of 24
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (1)
R1
R2
R3
R4
R5
R7
R8
R9
R10
R11
R12
R13
R14
ABP1
ABP2
LDP
TMB
BSC1
R6
CONTROL
BITS
BAND
SELECT
CLOCK
ANTI-
BACKLASH
PULSE
WIDTH
14-BIT REFERENCE COUNTER
DB21
DB22
DB23
L
D
P
T
M
B
R
R
BSC2
RSV
RSV
TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.
R14
0
0
0
0
.
.
.
1
1
1
1
R13
0
0
0
0
.
.
.
1
1
1
1
R12
0
0
0
0
.
.
.
1
1
1
1
R3
0
0
0
1
.
.
.
1
1
1
1
R2
0
1
1
0
.
.
.
0
0
1
1
R1
1
0
1
0
.
.
.
0
1
0
1
DIVIDE RATIO
1
2
3
4
.
.
.
16380
16381
16382
16383
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
THESE BITS ARE NOT
USED BY THE DEVICE
AND ARE DON'T CARE
BITS.
0
LDP
0
LOCK DETECT PRECISION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
ABP2
0
0
1
1
ABP1
0
1
0
1
ANTIBACKLASH PULSE WIDTH
3.0ns
1.3ns
6.0ns
3.0ns
BSC2
0
0
1
1
BSC1
0
1
0
1
BAND SELECT CLOCK DIVIDER
1
2
4
8
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