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參數(shù)資料
| 型號： | AD4360-8 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | Integrated Synthesizer and VCO |
| 中文描述： | 綜合合成器和VCO |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 332K |
| 代理商： | AD4360-8 |
ADF4360-8
OUTPUT STAGE
The RF
OUT
A and RF
OUT
B pins of the ADF4360 family are
connected to the collectors of an NPN differential pair driven
by buffered outputs of the VCO, as shown in Figure 20. To allow
the user to optimize the power dissipation vs. the output power
requirements, the tail current of the differential pair is pro-
grammable via Bits PL1 and PL2 in the control latch. Four cur-
rent levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA. These
levels give output power levels of 9 dBm, 6 dBm, 3 dBm,
and 0 dBm, respectively, using the correct shunt inductor to V
DD
and ac coupling into a 50 load. Alternatively, both outputs can
be combined in a 1 + 1:1 transformer or a 180° microstrip cou-
pler (see the Output Matching section).
Rev. A | Page 12 of 24
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to V
DD
.
Another feature of the ADF4360 family is that the supply current
to the RF output stage is shut down until the part achieves lock, as
measured by the digital lock detect circuitry. This is enabled by the
Mute-Till-Lock Detect (MTLD) bit in the control latch.
VCO
RF
OUT
A
RF
OUT
B
BUFFER
0
Figure 20. Output Stage ADF4360-8
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