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參數(shù)資料
| 型號(hào)： | AD28msp01KST⒂ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PSTN Signal Port |
| 中文描述： | PSTN的信號(hào)端口 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 368K |
| 代理商： | AD28MSP01KST⒂ |
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AD28msp01
REV. A
–21–
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured out-
put high or low voltage to a high-impedance state. The output
disable time (t
DIS
) is the difference of t
MEASURED
and t
DECAY
, as
shown in the Output Enable/Disable diagram. The time,
t
MEASURED
, is the interval from when a reference signal reaches a
high or low voltage level to when the output voltages have
changed by 0.5 V from the measured output high or low volt-
age. The decay time, t
DECAY
, is dependent on the capacitive
load, C
L
, and the current load, i
L
, on the output pin. It can be
approximated by the following equation:
t
DECAY
=
C
L
×
0.5
V
i
L
from which
t
DIS
=
t
MEASURED
– t
DECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start driv-
ing. The output enable time (t
ENA
) is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
V
+ 0.5V
OL
(MEASURED)
V
OH
– 0.5V
(MEASURED)
REFERENCE
SIGNAL
OUTPUT
V
OH
(MEASURED)
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS
VOLTAGE LEVEL TO BE APPROXIMATELY 1.5 V.
t
ENA
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
MEASURED
t
2.0V
1.0V
DECAY
t
OH
(MEASURED)
V
(MEASURED)
OL
V
t
DIS
V
OL
(MEASURED)
Figure 18. Output Enable/Disable
Serial Ports
Parameter
Min
Max
Unit
Timing Requirement:
t
SCS
t
SCH
Switching Characteristic:
t
RD
t
RH
t
SCDH
t
SCDD
SDI/SDIFS Setup before SCLK Low
SDI/SDIFS Hold after SCLK Low
10
15
ns
ns
SDOFS Delay from SCLK High
SDOFS Hold after SCLK High
SDO Hold after SCLK High
SDO Delay from SCLK High
30
ns
ns
ns
ns
0
0
30
SCLK
SDIFS
SDI
MSB
2ND MSB
3RD MSB
SDOFS
SDO
t
RD
t
SCS
t
SCH
t
SCK
t
RH
t
SCDD
t
SCS
t
SCH
t
SCDH
Figure 19. Serial Ports
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD28MSP01KP | PSTN Signal Port |
| AD28MSP01KR | PSTN Signal Port |
| AD28MSP02 | RD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 15V; Power: 2W; Low Cost 2W Dual Output Converter; Industry Standard SIP7 and DIP14 Packages; Power Sharing on Outputs; Optional Continuous Short Circuit Protected; 1kVDC & 2kVDC Isolation Options; UL94V-0 Package Material; Efficiency to 86% |
| AD28MSP02BN | Voiceband Signal Port |
| AD28MSP02BR | Voiceband Signal Port |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD28MSP01KST⒂ | 制造商:AD 制造商全稱:Analog Devices 功能描述:PSTN Signal Port |
| AD28MSP02 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Voiceband Signal Port |
| AD28MSP02BN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD28MSP02BR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD28MSP02KN | 制造商:AD 制造商全稱:Analog Devices 功能描述:Voiceband Signal Port |
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