參數(shù)資料
型號: AD28msp01KST⒂
廠商: Analog Devices, Inc.
英文描述: PSTN Signal Port
中文描述: PSTN的信號端口
文件頁數(shù): 15/28頁
文件大?。?/td> 368K
代理商: AD28MSP01KST⒂
AD28msp01
REV. A
–15–
FROM MODEM TX
TO MODEM RX
AD28msp01
A/D
DATA
REGISTER 2
CONTROL
REGISTER 4
RX PHASE ADJUST
ANALOG IN
MCLK
16
16
DSP Processor
D/A
DATA
REGISTER 0
16
ANALOG OUT
TCONV
TBIT
TBAUD
PHASE ADJUST
TX CLOCKS
TX CLOCKS
RX CLOCKS
RCONV
RBIT
RBAUD
PHASE ADJUST
CONVERT
START
CONVERT
START
CONTROL
REGISTER 5
TX PHASE ADJUST
16
Figure 11. Asynchronous Fallback Mode Block Diagram
Operating Mode Summary
Table III summarizes the operating modes.
Table III. Operating Mode Summary
Internal Filter
Operation
Synchronous To:
ADC
Initial Phase
Lock After
Entering Mode
Phase Adjust
Control
Register 0
OP 2-0
Normal DPLL* Register
Operation
Resampling
Interpolator
Mode
Programmable
DAC
Async Fallback
no phase lock
no phase lock
RCV, TX
not used
RCONV
TCONV
0 0 0
Async TSYNC
TCONV lock
to TSYNC
TCONV lock
to TSYNC
RCV
not used
RCONV
TCONV
1 1 1
V.32 TSYNC
RCONV lock
to TCONV
TCONV lock
to TSYNC
RCV
Input synchronous
and in phase with
TCONV, Output
synchronous and in
phase with RCONV
TCONV
TCONV
1 0 0
V.32 Internal Sync RCONV lock
no phase lock
RCV, TX
Input synchronous
and in phase with
TCONV, Output
synchronous and in
phase with RCONV
TCONV
TCONV
1 0 1
to TCONV
V.32 Loopback
TCONV lock
to RCONV
no phase lock
RCV
not used
TCONV
TCONV
1 1 0
NOTES
*DPLL—Digital Phase-Locked loop.
RCV phase adjusted via Control Register 4, TX phase adjusted via Control Register 5.
Adjusting RCV phase also adjusts TX phase in this mode.
Note: All receive clocks: RBIT, RBAUD are synchronous to RCONV. All transmit clocks: TBIT, TBAUD are synchronous to TCONV.
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AD28MSP01KST⒂ 制造商:AD 制造商全稱:Analog Devices 功能描述:PSTN Signal Port
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