
AD280
–5–
REV. 0
PRELMNARY
Data Input for the Serial Interface.
Data Output from the Serial Interface. In a three-state condition unless a data read command is
being executed.
Chip Enable Input. This signal is used to frame each byte of a command or data transfer.
Shift Clock Input. This signal clocks data to/from the AD280 via the serial interface.
DOUT0–DOUT3
General purpose digital inputs, accessible via the serial interface.
C3
Connection for the shunt capacitor required by the charge pump circuit (nominally 1
μ
F/10V
tantalum, low ESR (Effective Series Resistance), negative terminal connected to Pin 38).
C2, C1
Connections for the series capacitor required by the charge pump (nominally 1
μ
F/10 V tanta-
lum, low ESR (Effective Series Resistance), negative terminal connected to Pin 39).
DGND
Digital Ground.
DVDD
Power supply input for digital portion of the AD280. Nominally +5 V
±
5%.
TECHNCAL
PIN FUNCTION DESCRIPTION
Description
Pin #
Pin Name
1
CPE
Charge Pump Enable. When tied to a Logic “1,” enables the internal charge pump within the
AD280, allowing single supply operation.
Buffered Output from the Crystal Oscillator.
Connection for External Crystal.
Connection for External Crystal.
Positive power supply connection for analog circuit; nominally +5 V
±
5%.
Negative Power Supply Connection; tied externally to C3 (Pin 38) Nominally –5 V
±
5%
supplied externally if charge pump is not used (see Pin 1)
Connection for external resistor, which sets the magnitude of the current used for RTD excitation.
Excitation outputs used to supply open circuit detection current (all four) or RTD excitation
current (EXC0 and EXC1 only).
Analog Input Channels; single-ended inputs with respect to analog ground.
Reference Voltage Output. Nominally +2.5 V.
Reference Voltage Input. Nominally connected to REFOUT.
Cold Junction Compensation Sensor Input. Can be connected to a thermistor or silicon tem-
Ground Sense Input. Used for measuring ground to compensate for ground loops or other
offsets.
Analog Ground. All input signals are referenced to this pin.
Output of the Programmable Gain Amplifier; supplied primarily for test and diagnostic purposes.
Connection for External Integration Capacitor; Nominally 4.7 nF.
Reset Input to Internal Logic. When at Logic “0,” forces internal logic into the command mode
condition. Normally connected to a power-up reset circuit or RC reset circuit.
General purpose digital inputs, accessible via the serial interface.
Data Ready Output. When at Logic “1,” indicates that the most recent A/D conversion is com-
plete and that data is available. This signal is also available via the serial interface, located in the
status byte.
2
3
4
5
6
XTALOUT
XTAL1
XTAL2
AVDD
ALO
7
8, 9, 10, 11
ISET
EXC0–EXC3
12–15
16
17
18
AIN0–AIN3
REFOUT
REFIN
CJCIN
19
GND SENSE
20
21
22, 23
24
AGND
PGAOUT
CINT1, CINT2
RESET
25–28
29
DIN3–DIN0
DRDY
30
31
DI
DO
32
33
34–37
38
CE
SK
39, 41
40
42