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參數(shù)資料
| 型號： | AD280 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Universal Multichannel Industrial Signal Conditioning ADC(通用,多通道,工業(yè)信號調(diào)節(jié)A/D轉(zhuǎn)換器) |
| 中文描述： | 工業(yè)通用多通道ADC的信號調(diào)理（通用，多通道，工業(yè)信號調(diào)節(jié)的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 150K |
| 代理商： | AD280 |
–11–
REV. 0
AD280
NO OPERATION
None
WRITE CFG0
1
WRITE CFG1
WRITE CFG0/CFG1
2
WRITE CFG2
1
WRITE CFG3
1
WRITE CFG4
1
WRITE CFG2/CFG3/CFG4
3
START CONVERSION
None
TECHNCAL
DATA
out the need to transmit a command byte for each register. The
command code specifies the number of bytes that follow. Up to
three bytes of data, in ascending order, may be transferred after
the command byte. This capability substantially reduces the
time required to access the AD280, since in most cases the
register groupings will always be read or written together. It is
important to note that in all cases, regardless of whether single
or multiple byte mode is used, each byte transferred will require
the complete sequence of the
CE
(Chip Enable) and SK (Shift
Clock) pins.
Table III. Command Codes and Corresponding Functions
Command Code
CC3 CC2 CC1 CC0 Function
Parameter
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
NO OPERATION
READ STATUS
READ DATA0
READ DATA1
READ DATA2
READ DATA0/DATA1/DATA2
NO OPERATION
None
1
1
1
1
3
None
The four “read” registers in the AD280 consist of three data
bytes (DATA0, DATA1, DATA2) and a STATUS byte. The
three data bytes constitute a 24-bit twos-complement binary
integer that is proportional to the signal data. The status byte
contains the auxiliary digital input data, along with an image of
the DRDY signal, which is a copy of the separate external
DRDY line.
The data bytes and status byte may be read at any time. If read
during an A/D conversion, the data bytes will contain the results
of the LAST conversion completed. They will not be updated
with the NEW conversion data until the next conversion is com-
plete. The user is responsible for reading the data when it is
valid. The data is valid after one conversion is complete (i.e.,
when DRDY goes high), and remains valid until the next con-
version is complete. The data must be read early enough in the
conversion cycle to assure that it is not updated during the
data transfer. Normally, it is most efficient to use the follow-
ing sequence:
NA
NA
NA
NA
MSB
LSB
C0
CMD:
C3
C2
C1
CJC
EXC
PGA2
MSB
LSB
CFG4:
PGA1 PGA0 MUX2 MUX1 MUX0
D
OUT
MSB
LSB
CFG3:
D
OUT
D
OUT
D
OUT
ATTEN
ATTEN
CH2
ATTEN
CH1
ATTEN
CH0
EXC3
HI
MSB
LSB
CFG2:
EXC3
LO
EXC2
HI
EXC2
LO
EXC1
HI
EXC1
LO
EXC0
LO
EXC0
HI
T
MSB
BIT
14
MSB
LSB
CFG1:
BIT
13
BIT
12
BIT
11
BIT
10
BIT
9
BIT
8
MSB
LSB
T
LSB
CFG0:
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
DIN
3
DRDY
NA
NA
NA
MSB
LSB
STATUS:
DIN
2
DIN
1
DIN
0
DATA
MSB
BIT
22
MSB
LSB
DATA2:
BIT
21
BIT
20
BIT
19
BIT
18
BIT
17
BIT
16
MSB
LSB
DATA1:
BIT
15
BIT
14
BIT
13
BIT
12
BIT
11
BIT
10
BIT
9
BIT
8
MSB
LSB
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
BIT
7
DATA
LSB
DATA0:
NA
WRITEABLE REGISTERS
READABLE REGISTERS
Figure 10. AD280 Internal Registers
1. Wait for the conversion to complete.
3. Wait for settling of the MUX and PGA (1 mS max). Read
the data from the previous conversion while waiting.
4. Trigger the A/D for the next conversion.
All AD280 registers may be read or written in a “single byte”
mode by using the appropriate commands. In the single byte
mode, the command code specifies which individual register is
to be read or written. The byte must be read or written immedi-
ately after the command code is sent to the AD280.
In addition to byte-at-a-time access, “multiple byte” mode
allows certain register combinations to be read or written with-
SETTING THE A/D INTEGRATION PERIOD
The integration period of the AD280’s A/D converter is set by
writing to the CONFIG0 and CONFIG1 registers. These two
bytes constitute a 16-bit binary integer which represents the
upper 16 bits of a 21-bit counter clocked by the AD280’s clock.
The formula for the integration period is:
D
CONFIG0/1
= (
F
CLK
×
T
INT
)/32
where
D
CONFIG0/1
represents a 16-bit integer. For example, when
using a 10 MHz clock frequency, and when an integration
period of 16.666 ms is desired, the required integer is 5209
10
,
or 1459
16
. Practical integration periods range from 1 ms to
200 ms, depending upon clock speed.
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