
AD280
–12–
REV. 0
C
P
PRELMNARY
TECHNCAL
DATA
44-Lead Metric Plastic Quad Flatpack (MQFP)
(S-44)
(PINS DOWN)
12
44
1
11
22
23
34
33
0.45 (0.018)
0.3 (0.012)
13.45 (0.529)
12.95 (0.510)
10.1 (0.398)
9.90 (0.390)
8.45 (0.333)
8.3 (0.327)
0.8 (0.031)
BSC
2.1 (0.083)
1.95 (0.077)
0.23 (0.009)
0.13 (0.005)
0.25 (0.01)
MIN
SEATING
PLANE
0
MIN
2.45 (0.096)
MAX
1.03 (0.041)
0.73 (0.029)
The accuracy of the integration period is limited by the clock
speed and resolution of the CONFIG0/1 registers; faster clock
frequencies will result in more accurate integration periods, with
corresponding improvement in normal mode rejection.
A/D RESOLUTION
The resolution of the A/D converter is dependent upon the
integration period and the clock speed. For a given integration
period, the nominal full-scale output of the A/D will be
±
50%
of the number of clock cycles that occur in the integration
period. For example, a clock speed of 10 MHz and an integra-
tion period of 10 ms will produce an output of approximately
±
50,000 counts. All ranges have an overrange capability of
(typically) 20%, so the A/D will typically remain linear up to
±
60,000 counts (in the example just illustrated). The exception
to this overrange capability is when the attenuators are used to
achieve a 10 V input range; in this case, the special ESD circuits
will clamp the input at approximately
±
11 volts, thereby reduc-
ing the overrange to 10%.
EVALUATION KIT
An evaluation kit, consisting of an evaluation board with an
AD280 and support components is available (Part Number
AD280-ED). This kit includes a software demo program written
to operate under Windows
95.
Windows is a registered trademark of Microsoft Corporation.
OUTLINE DIMENSIONS
Dimensions shown in mm and (inches).