參數(shù)資料
型號(hào)： AD1953YSTZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/36頁(yè)
文件大?。?/td> 0K
描述： IC DSP DAC AUDIO3CH/26BIT 48LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 2,000
系列： SigmaDSP®
位數(shù)： 26
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 3
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 540mW
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 6 電壓，單極
采樣率（每秒）： 48k
REV. 0
AD1953
–30–
SERIAL DATA INPUT/OUTPUT PORTS
The AD1953’s flexible serial data input port accepts data in twos
complement, MSB first format. The left channel data field always
precedes the right channel data field. The serial mode is set by
using mode select bits in the SPI control register. In all modes
except for the right-justified mode, the serial port will accept an
arbitrary number of bits up to a limit of 24 (extra bits will not
cause an error, but they will be truncated internally). In the right-
justified mode, SPI control register bits are used to set the word
length to 16, 20, or 24 bits. The default on power-up is 24-bit mode.
Proper operation of the right-justified mode requires that there
be exactly 64 BCLK per audio frame.
Serial Data Input/Output Modes
Figure 19 shows the serial input modes. For the left-justified
mode, LRCLK is HIGH for the left channel, and LOW for the
right channel. Data is sampled on the rising edge of BCLK. The
MSB is left-justified to an LRCLK transition, with no MSB delay.
The left-justified mode can accept any word length up to 24 bits.
In I
2S mode, LRCLK is low for the left channel and high for the
right channel. Data is valid on the rising edge of BCLK. The MSB
is left-justified to an LRCLK transition but with a single BCLK
period delay. The I
2S mode can be used to accept any number
of bits up to 24.
In right-justified mode, LRCLK is high for the left channel and
low for the right channel. Data is sampled on the rising edge
of BCLK. The start of data is delayed from the LRCLK edge
by 16, 12, or 8 BCLK intervals, depending on the selected
word length. The default word length is 24 bits; other word
lengths are set by writing to Bits <1:0> of Control Register 1.
In right-justified mode, it is assumed that there are 64 BCLKs
per frame.
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
SDATA
LSB
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
DSP MODE – 16 BITS TO 24 BITS PER CHANNEL
NOTES
1. DSP MODE DOESN’T IDENTIFY CHANNEL
2. LRCLK NORMALLY OPERATES AT
fS EXCEPT DSP MODE, WHICH IS 2
fS
3. BCLK FREQUENCY IS NORMALLY 64
LRCLK BUT MAY BE OPERATED IN BURST MODE
I2S MODE – 16 BITS TO 24 BITS PER CHANNEL
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
1/
fS
LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL
MSB
Figure 19. Serial Input Modes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1953YSTZRL7 功能描述:IC DSP AUDIO 3CHAN 26BIT 48LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類(lèi)型:1 電流，單極；1 電流，雙極 采樣率（每秒）:*
AD1954 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:SigmaDSP⑩ 3-Channel, 26-Bit Signal Processing DAC
AD1954YS 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:THREE CHANNEL, 24-BIT SIGMADSP DAC - Bulk
AD1954YSRL 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 44-Pin MQFP T/R
AD1954YST 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:THREE CHANNEL, 24-BIT SIGMADSP DAC - Tape and Reel
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