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參數(shù)資料
| 型號： | AD1953YSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP DAC AUDIO3CH/26BIT 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | SigmaDSP® |
| 位數(shù)： | 26 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 540mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 6 電壓，單極 |
| 采樣率（每秒）： | 48k |
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REV. 0
AD1953
–23–
Volume Registers
The AD1953 contains eight 22-bit volume registers, one each
for the left, right, and subwoofer channels and an additional five
registers to be used by custom programs used in multichannel
applications. These registers are special because when the volume
is changed from an initial value to a new value, a linear ramp is
used to interpolate between the two values. This feature prevents
audible clicks and pops when changing volume. The ramp is
set so that it takes 512 audio frames to decrement from a volume of
1.0 (default) down to 0 (muted). The volume registers are for-
matted in 2.20 twos complement, meaning that 010000000
0000000000000 is interpreted as 1.0. Negative values can also be
written to the volume register, causing an inversion of the signal.
Negative values work as expected with the ramp feature; to go
from +1.0 to –1.0 will take 1024 LRCLKs, and the volume will
pass through 0 on the way.
Parameter RAM Contents
Table VI shows the contents of the parameter RAM. The
parameter RAM is 22 bits wide and occupies SPI addresses
0–255. The low addresses of the RAM are used to control the
biquad filters. There are 22 biquad filters in all, and each
biquad has five coefficients, resulting in a total memory usage
of 110 coefficients. There are also two tables of 33 coefficients
each that define the main and sub compressor input/output
characteristics. These are loaded with 1.0 on power-up, resulting
in no compression. Other RAM entries control other compressor
characteristics, as well as delay and spatialization settings.
The parameter RAM is initialized on power-up by an on-board
boot ROM. The default values (shown in the table) yield no
equalization, no compression, no spatialization, no delay, and
“normal” detector time constants in the compressor sections.
The functionality of the AD1953 on power-up is basically that
of a normal audio DAC with no signal-processing capability.
The data format of the Parameter RAM is twos complement
2.20 format. This means that the coefficients may range from
+2.0 (–1 LSB) to –2.0, with 1.0 represented by the binary word
0100000000000000000000.
Table VI. Parameter RAM Contents
Default Value
in Fractional
Address
Function
2.20 Format
0
IIR0 Left b0
1.0
1
IIR0 Left b1
0
2
IIR0 Left b2
0
3
IIR0 Left a1
0
4
IIR0 Left a2
0
5
IIR1 Left b0
1.0
6
IIR1 Left b1
0
7
IIR1 Left b2
0
8
IIR1 Left a1
0
9
IIR1 Left a2
0
10
IIR2 Left b0
1.0
11
IIR2 Left b1
0
12
IIR2 Left b2
0
13
IIR2 Left a1
0
14
IIR2 Left a2
0
15
IIR3 Left b0
1.0
16
IIR3 Left b1
0
17
IIR3 Left b2
0
18
IIR3 Left a1
0
19
IIR3 Left a2
0
20
IIR4 Left b0
1.0
21
IIR4 Left b1
0
22
IIR4 Left b2
0
23
IIR4 Left a1
0
24
0
25
IIR5 Left b0
1.0
26
IIR5 Left b1
0
27
IIR5 Left b2
0
28
IIR5 Left a1
0
29
IIR5 Left a2
0
30
IIR6 Left b0
1.0
31
IIR6 Left b1
0
32
IIR6 Left b2
0
33
IIR6 Left a1
0
34
IIR6 Left a2
0
35
IIR0 Right b0
1.0
Table VI. Parameter RAM Contents (continued)
Default Value
in Fractional
Address
Function
2.20 Format
36
IIR0 Right b1
0
37
IIR0 Right b2
0
38
IIR0 Right a1
0
39
IIR0 Right a2
0
40
IIR1 Right b0
1.0
41
IIR1 Right b1
0
42
IIR1 Right b2
0
43
IIR1 Right a1
0
44
IIR1 Right a2
0
45
IIR2 Right b0
1.0
46
IIR2 Right b1
0
47
IIR2 Right b2
0
48
IIR2 Right a1
0
49
IIR2 Right a2
0
50
IIR3 Right b0
1.0
51
IIR3 Right b1
0
52
IIR3 Right b2
0
53
IIR3 Right a1
0
54
IIR3 Right a2
0
55
IIR4 Right b0
1.0
56
IIR4 Right b1
0
57
IIR4 Right b2
0
58
IIR4 Right a1
0
59
IIR4 Right a2
0
60
IIR5 Right b0
1.0
61
IIR5 Right b1
0
62
IIR5 Right b2
0
63
IIR5 Right a1
0
64
IIR5 Right a2
0
65
IIR6 Right b0
1.0
66
IIR6 Right b1
0
67
IIR6 Right b2
0
68
IIR6 Right a1
0
69
IIR6 Right a2
0
70
IIR0 Xover Left b0
1.0
71
IIR0 Xover Left b1
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1953YSTZRL7 | 功能描述:IC DSP AUDIO 3CHAN 26BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD1954 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP⑩ 3-Channel, 26-Bit Signal Processing DAC |
| AD1954YS | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:THREE CHANNEL, 24-BIT SIGMADSP DAC - Bulk |
| AD1954YSRL | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 44-Pin MQFP T/R |
| AD1954YST | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:THREE CHANNEL, 24-BIT SIGMADSP DAC - Tape and Reel |
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