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參數(shù)資料
| 型號： | AD1891JP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SamplePort Stereo Asynchronous Sample Rate Converters |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 416K |
| 代理商： | AD1891JP |
AD1890/AD1891
–4–
REV. 0
(continued from Page 1)
PRODUCT OVE RVIE W (Continued)
automatically limited to avoid alias distortion on the output sig-
nal. T he AD1890/AD1891 dynamically alter the low-pass filter
cutoff frequency smoothly and slowly, so that real-time varia-
tions in the sample rate ratio are possible without degradation of
the audio quality.
T he AD1890/AD1891 have a pin selectable slow- or fast-settling
mode. T his mode determines how quickly the ASRCs adapt to a
change in either the input sample clock frequency (F
SIN
) or the
output sample clock frequency (F
SOUT
). In the slow-settling
mode, the control loop which computes the ratio between F
SIN
and F
SOUT
settles in approximately 800 ms and begins to reject
jitter above 3 Hz. T he slow-settling mode offers the best signal
quality and the greatest jitter rejection. In the fast-settling mode,
the control loop settles in approximately 200 ms and begins to
reject jitter above 12 Hz. T he fast-settling mode allows rapid,
real time sample rate changes to be tracked without error, at the
expense of some narrow-band noise modulation products on the
output signal.
T he AD1890 also has a pin selectable, short or long group delay
mode. T his pin determines the depth of the First-In, First-Out
(FIFO) memory which buffers the input data samples before
they are processed by the FIR convolver. In the short mode, the
group delay is approximately 700
μ
s. T he ASRC is more sensi-
tive to sample rate changes in this mode (i.e., the pointers which
manage the FIFO are more likely to cross and become momen-
tarily invalid during a sample rate step change), but the group
delay is minimized. In the long mode, the group delay is ap-
proximately 3 ms. T he ASRC is tolerant of large dynamic
sample rate changes in this mode, and it should be used when
the device is required to track fast sample rate changes, such as
in varispeed applications. T he AD1891 features the short group
delay mode only. In either device, if the read and write pointers
that manage the FIFO cross (indicating underflow or overflow),
the ASRC asserts the mute output (MUT E_O) pin HI for 128
output clock cycles. If MUT E_O is connected to the mute input
(MUT E_I) pin, as it normally should be, the serial output will
be muted (i.e., all bits zero) during this transient event.
T he AD1890/AD1891 are fabricated in a 0.8
μ
m single poly,
double metal CMOS process and are packaged in a 0.6" wide
28-pin plastic DIP and a 28-pin PLCC. T he AD1890/AD1891
operate from a +5 V power supply over the temperature range of
0
°
C to +70
°
C.
28
27
26
22
21
20
19
18
17
25
24
23
16
15
SERIAL IN
SERIAL OUT
MULT
CLOCK
TRACKING
ACCUM
RESET
LR_I
LR_O
1
2
3
7
8
9
10
11
12
4
5
6
13
14
COEF ROM
FIFO
GPDLYS (AD1890)
N/C (AD1891)
MCLK
DATA_I
BCLK_I
WCLK_I
V
DD
GND
N/C
BKPOL_I
TRGLR_I
MSBDLY_I
GND
SETSLW
GND
BCLK_O
WCLK_O
DATA_O
V
DD
GND
N/C
BKPOL_O
TRGLR_O
MSBDLY_O
MUTE_O
MUTE_I
AD1890/AD1891
N/C = NO CONNECT
AD1890/AD1891 DIP Pinout
22
21
20
19
25
24
23
7
8
9
10
11
5
6
LR_I
LR_O
SERIAL IN
R
SERIAL OUT
ACCUM
COEF ROM
FIFO
MULT
N/C
WCLK_I
V
DD
GND
BKPOL_I
TRGLR_I
WCLK_O
DATA_O
V
DD
GND
N/C
BKPOL_O
1
2
3
4
28
27
26
12
13
14
18
17
16
15
G
N
M
D
B
S
G
B
M
G
T
M
M
M
CLOCK
TRACKING
AD1890/AD1891
N/C = NO CONNECT
AD1890/AD1891 PLCC Pinout
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| AD1892 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Digital Receiver/Rate Converter |
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| AD1892JRRL | 制造商:Analog Devices 功能描述:Receiver/Rate Converter 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:INTEGRATED DIG.RECEIVER/RATE CONVERTER - Bulk |
| AD1892JRZ | 制造商:Analog Devices 功能描述:Receiver/Rate Converter 28-Pin SOIC W |
| AD1893 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter |
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