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參數(shù)資料
| 型號： | AD1891JP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | SamplePort Stereo Asynchronous Sample Rate Converters |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 416K |
| 代理商： | AD1891JP |
AD1890/AD1891
REV. 0
–19–
BCLK_I, BCLK_O
NORMAL MODE
BCLK_I, BCLK_O
INVERTED MODE
INPUT
DATA IN/OUT
NO MSB DELAY MODE
MSB–2 MSB–3
LEFT DATA
MSB
MSB-1
RIGHT DATA
LSB+1
LSB
MSB-3
MSB
MSB-1 MSB-2
LSB
DATA IN/OUT
MSB DELAY MODE
MSB
MSB–1 MSB–2
LEFT DATA
MSB
LSB
LSB+1
LSB+2
MSB-1 MSB-2
RIGHT DATA
LSB+1
LSB
LR_I, LR_O
INPUT
Figure 23. AD1890/AD1891 Serial Data Input and Output Timing, Left/
Right
Clock Triggered Mode
MCLK
t
RS
t
RPWL
RESET
Figure 25. AD1890/AD1891 Reset Timing
MCLK
t
MCLK
t
MPWL
t
MPWH
Figure 24. AD1890/AD1891 MCLK Timing
t
DH
NORMAL MODE
BCLK_I, BCLK_O
INVERTED MODE
WCLK_I
WCLK_O
t
BPWH
MSB
MSB-1
DATA IN
NO MSB DELAY MODE
DATA OUT
NO MSB DELAY MODE
DATA IN
MSB DELAY MODE
DATA OUT
MSB DELAY MODE
t
DOH
MSB
MSB
MSB-1
t
BPWL
t
BPWL
t
BPWH
t
LRSO
t
DS
t
LRSI
t
WSO
t
WSI
t
DH
t
DPD
MSB-1
MSB
t
DS
t
DOH
MSB-1
t
DPD
LR_I
LR_O
Figure 26. AD1890/AD1891 Bit Clock, Word Clock, Left/
Right
Clock and Data Timing
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| AD1892 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Digital Receiver/Rate Converter |
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| AD1893 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter |
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